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DAC8420FS датащи(PDF) 6 Page - Analog Devices |
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DAC8420FS датащи(HTML) 6 Page - Analog Devices |
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6 / 16 page ![]() DAC8420 REV. 0 –6– PIN CONFIGURATIONS PIN FUNCTION DESCRIPTION Power Supplies VDD: Positive Supply, +5 V to +15 V. VSS: Negative Supply, 0 V to –15 V. GND: Digital Ground. Clock CLK: System Serial Data Clock Input, TTL/CMOS levels. Data presented to the input SDI is shifted into the internal serial-parallel input register on the rising edge of clock. This input is logically ORed with CS. Control Inputs (All are CMOS/TTL compatible.) CLR : Asynchronous Clear, active low. Sets internal data registers A-D to zero or midscale, depending on cur- rent state of CLSEL. The data in the serial input shift register is unaffected by this control. CLSEL: Determines action of CLR. If HIGH, a Clear command will set the internal DAC registers A-D to midscale (800H). If LOW, the registers are set to zero (000H). CS : Device Chip Select, active low. This input is logically ORed with the clock and disables the serial data register input when HIGH. When LOW, data input clocking is enabled, see the Control Function Table. LD : Asynchronous DAC Register Load Control, active low. The data currently contained in the serial input shift register is shifted out to the DAC data registers on the falling edge of LD, independent of CS. Input data must remain stable while LD is LOW. Data Input (All are CMOS/TTL compatible.) SDI: Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register, which shifts data in beginning with DAC address Bit A1. This input is ignored when CS is HIGH. The format of the 16-bit serial word is: (FIRST) (LAST) B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 A1 A0 NC NC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 —Address Word— (MSB) —DAC Data Word— (LSB) NC = Don’t Care. Reference Inputs VREFHI: Upper DAC ladder reference voltage input. Allowable range is (VDD – 2.5 V) to (VVREFLO +2.5 V). VREFLO: Lower DAC ladder reference voltage input, equal to zero scale output. Allowable range is VSS to (VVREFHI – 2.5 V). Analog Outputs VOUTA through VOUTD: Four buffered DAC voltage outputs. DIP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 TOP VIEW (Not to Scale) DAC8420 VDD VOUTD VOUTC VREFLO VREFHI VOUTB VOUTA VSS CLSEL NC CLK SDI GND CLR LD CS NC = NO CONNECT SOL 1 2 3 4 8 7 6 5 TOP VIEW (Not to Scale) DAC-8420 TOP VIEW (Not to Scale) DAC-8420 9 16 15 14 13 12 11 10 NC = NO CONNECT VDD VOUTD VOUTC VREFLO VREFHI VOUTB VOUTA VSS CLSEL NC CLK SDI GND CLR LD CS TOP VIEW (Not to Scale) DAC8420 |
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