DAC8420

REV. 0

–7–

Table I. Control Function Logic Table

CLK

1

CS

1

LD

CLR

CLSEL

Serial Input Shift Register

DAC Registers A-D

NC

H

H

L

H

No Change

NC

H

H

L

L

No Change

NC

H

H

↑

H/L

No Change

Latches Value

↑

L

H

H

NC

Shifts Register One Bit

No Change

L

↑

H

H

NC

Shifts Register One Bit

No Change

H

NC (

↑)

↓

H

NC

No Change

Loads the Serial Data Word

2

H

NC

L

H

NC

No Change

Transparent

3

NC

H

H

H

NC

No Change

No Change

NC = Don’t Care.

NOTES

OPERATION

Introduction

The DAC8420 is a quad, voltage-output 12-bit DAC with serial

digital input, capable of operating from a single +5 V supply.

The straightforward serial interface can be connected directly to

most popular microprocessors and microcontrollers, and can ac-

cept data at a 10 MHz clock rate when operating from

±15 V

supplies. A unique voltage reference structure assures maximum

utilization of DAC output resolution by allowing the user to set

the zero- and full-scale output levels within the supply rails. The

analog voltage outputs are fully buffered, and are capable of

driving a 2 k

Ω load. Output glitch impulse during major code

transitions is a very low 64 nV-s (typ).

Digital Interface Operation

The serial input of the DAC-8420, consisting of CS, SDI, and

LD

, is easily interfaced to a wide variety of microprocessor serial

ports. As shown in Table I and the Timing Diagram, while CS

is LOW the data presented to the input SDI is shifted into the

internal serial/parallel shift register on the rising edge of the

clock, with the address MSB first, data LSB last. The data for-

mat, shown above, is two bits of DAC address and two “don’t

care” fill bits, followed by the 12-bit DAC data word. Once all

16 bits of the serial data word have been input, the load control

LD

is strobed and the word is parallel-shifted out onto the inter-

nal data bus. The two address bits are decoded and used to

route the 12-bit data word to the appropriate DAC data regis-

ter, see the Applications Information.

Correct Operation of CS and CLK

As mentioned in Table I, the control pins CLK and CS require

some attention during a data load cycle. Since these two inputs

are fed to the same logical “OR” gate, their operation is in fact

identical. The user must take care to operate them accordingly

in order to avoid clocking in false data bits. As shown in the

Timing Diagram, CLK must be either halted HIGH, or CS

brought HIGH during the last HIGH portion of the CLK fol-

lowing the rising edge which latched in the last data bit. Other-

wise, an additional rising edge is generated by CS rising while

CLK is LOW, causing CS to act as the clock and allowing a

false data bit into the serial input register. The same issue must

be considered in the beginning of the data load sequence also.

Using CLR and CLSEL

The CLEAR (CLR) control allows the user to perform an asyn-

chronous reset function. Asserting CLR loads all four DAC data

word registers, forcing the DAC outputs to either zero-scale

shown in the Digital Function Table. The CLEAR function is

asynchronous and is totally independent of CS. When CLR

returns HIGH, the DAC outputs remain latched at the reset

value until LD is strobed, reloading the individual DAC data word

registers with either the data held in the serial input register prior

to the reset, or new data loaded through the serial interface.

Table II. DAC Address Word Decode Table

A1

A0

DAC Addressed

0

0

DAC A

0

1

DAC B

1

0

DAC C

1

1

DAC D

Programming the Analog Outputs

The unique differential reference structure of the DAC8420

allows the user to tailor the output voltage range precisely to the

needs of the application. Instead of spending DAC resolution

on an unused region near the positive or negative rail, the

DAC8420 allows the user to determine both the upper and

lower limits of the analog output voltage range. Thus, as shown

in Table III and Figure 1, the outputs of DACs A through D

range between VREFHI and VREFLO, within the limits speci-

fied in the Electrical Characteristics tables. Note also that

VREFHI must be greater than VREFLO.

1 LSB

2.5V MIN

2.5V MIN

0V MIN

–10V MIN

Figure 1. Output Voltage Range Programming