ADV7152LS85 datasheet(30/32 Pages) AD

30 / 32 page

ADV7152

–30–

REV. B

the graphics pipeline and after a number of clocks get latched

into the DAC Test Register. This data can then be read from

the Pixel Test Register and the DAC Test Registers over the

MPU Port. This data will remain in the Pixel Test Registers and

the DAC Test Registers until the next rising edge of R7 causes

new data to be latched in.

In the above example, the next rising edge of R7 occurs on the

Pixel n input. Therefore the data in the Pixel Test Registers and

DAC Test Registers must be read over the MPU before the

Pixel n data is applied, otherwise they will be overwritten by the

Pixel n data and the Pixel 2 data will be lost.

Pixel Test Register

The read-only Pixel Test Register is 24 bits wide, 8 bits each for

red, green and blue. It is situated directly after the Pixel Mask

R7, it is read in three cycles over the MPU Port as described in

the “Microprocessor (MPU) Port” section.

DAC Test Register

The DAC Test Register is latched with data some CLOCKs

after the Pixel Test Register. The DAC Test Register is a 30-bit

wide read-only register, corresponding to 10 bits each for red,

green and blue data. It is located the Color Palette RAM. If the

RAM-DAC is in 8-bit after resolution mode, the upper two bits

of the red, green and blue data will be zero. After data is latched

into the DAC Test Register by a transition on R7, it is read

in three or six cycles over the MPU Port as described in the

“Microprocessor (MPU) Port” section.

SYNC

, BLANK and IPLL Test Register

This is an 8-bit wide register but with only three effective bits.

The three lower bits correspond to SYNC, BLANK and IPLL

respectively. The upper bits should be masked in software. This

DAC Test Register. When pixel data is latched into the DAC

Test Register, the corresponding status of SYNC, BLANK and

IPLL is latched into this register. It is read over the MPU Port as

described in the “Microprocessor (MPU) Port” section.

(Note: If BLANK is low, the corresponding pixel data to the

DAC Test Register will be all “0s.”)

The ADV7152 contains onboard circuitry which enables both

device and system level test diagnostics. The test circuitry can

be used to test the frame buffer memory as well as the function-

ality of the ADV7152. A number of test registers are integrated

into the part which effectively allow for monitoring of the graph-

ics pipeline. Pixel data is read from the graphics pipeline inde-

pendent of the pixel CLOCK. The pixel data itself contains the

triggering information that latches data into the test registers.

This allows for system diagnostics in a continuously clocked

graphics system. The test register data is then read by the micro-

processor over the MPU.

Access to the test registers is as described in the “Microproces-

sor (MPU) Port” section. This section also gives the address

decode locations for the various test registers.

Test Trigger (R7)

The test trigger is decoded from the pixel data stream. Bit R7 of

the RED channel is assigned the task of latching pixel data into

the test registers. A “0” to “1” or a “1” to “0” (as determined

by bit CR20 of Command Register 2) transition on R7, fills the

test register with the corresponding pixel data. This effectively

means that a sequence of data travels along the graphics pipe-

line, with the test registers taking a sample only when there is a

transition on Bit R7. The following example shows a sequence

with the ADV7152 preset to sample the graphics pipeline on a

low to high transition of R7.

RED

GREEN

BLUE

Pixel 0:

00000000

Pixel 1:

0........

........

Pixel 2:

1........

........

Pixel 3:

0........

........

. ...

...

. ...

...

Pixel n-1:

0........

........

Pixel n:

1........

........

Pixel n:

0........

........

In the above sequence of pixels, there is a rising edge on R7 on

Pixel 2. The Red, Green and Blue data for Pixel 2, therefore,

gets latched into the Pixel Test Register. Pixel 2 continues down

APPENDIX 6

TEST DIAGNOSTICS

INPUT

MUX

PIXEL TEST

COLOR

REGISTERS

DAC TEST

REGISTERS

COLOR

PALETTE

RAM

DACs

TRIGGER

DECODE

PIXEL

DATA

BLANK

SYNC

D9–D0

R/W

TRIGGER

DECODE

GRAPHICS PIPELINE

MPU PORT

SYNC BLANK

IPLL TEST

Test/Diagnostic Block Diagram

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