ADV7152LS85 datasheet(18/32 Pages) AD

18 / 32 page

ADV7152

–18–

REV. B

The following section describes each register, including Address

in terms of its configuration.

Address Register (A7–A0)

As illustrated in the previous tables, the C0 and C1 control in-

puts, in conjunction with this address register specify which con-

trol register, or color palette location is accessed by the MPU

port. The address register is 8-bits wide and can be read from as

well as written to. When writing to or reading from the color

palette on a sequential basis, only the start address needs to be

written. After a red, green and blue write sequence, the address

MODE REGISTER MR1 (MR19–MR10)

The mode register is a 10-bit wide register. However for pro-

gramming purposes, it may be considered as an 8-bit wide regis-

ter (MR18 and MR19 are both reserved). It is denoted as

MR17–MR10 for simplification purposes.

The diagram shows the various operations under the control of

the mode register. This register can be read from as well written

to. In read mode, if MR18 and MR19 are read back, they are

both returned as zeros.

MODE REGISTER (MR17–MR10) BIT DESCRIPTION

Reset Control (MR10)

This bit is used to reset the pixel port sampling sequence. This

ensures that the pixel sequence AB starts at A. It is reset by writ-

ing a “1” followed by a “0” followed by a “1.” This bit must be

run through this cycle during the initialization sequence.

RAM-DAC Resolution Control (MR11)

When this is programmed with a “1,” the RAM is 30 bits deep

(10 bits each for red, green and blue) and each of the three

DACs is configured for 10-bit resolution. When MR11 is pro-

grammed with a “0,” the RAM is 24 bits deep (8 bits each for

red, green and blue) and the DACs are configured for 8-bit

resolution. The two LSBs of the 10-bit DACs are pulled down

to zero in 8-bit RAM-DAC mode.

MPU Databus Width (MR12)

This bit determines the width of the MPU port. It is configured

as either a 10-bit wide (D9–D0) or 8-bit wide (D7–D0) bus.

10-bit data can be written to the device when configured in

8-bit wide mode. The 8 MSBs are first written on D7–D0, then

the two LSBs are written over D1–D0. Bits D9–D8 are zeros in

8-bit mode.

Operational Mode Control (MR14–MR13)

When MR14 is “0” and MR13 is “1,” the part operates in

normal mode.

Calibrate LOADIN (MR15)

This bit automatically calibrates the onboard LOADIN/

LOADOUT synchronization circuit. A “0” to “1” transition

initiates calibration. This bit is set to “0” in normal operation.

See “Pipeline Delay and Calibration” section. This bit must be

run through this cycle during the initialization sequence.

Palette Select Match Bits Control (MR17–MR16)

These bits allow multiple palette devices to work together.

When bits PSI and PS0 match MR17 and MR16 respectively,

the device is selected. If these bits do not match, the device is

not selected and the analog video outputs drive 0 mA, see

“Palette Priority Select Inputs” section.

Control Registers

The ADV7152 has 9 control registers. To access each register,

two write operations must be performed. The first write to the

address register specifies which of the 9 registers is to be ac-

cessed. The second access determines the value written to that

particular control register.

Pixel Test Register

(Address Reg (A7–A0) = 00H)

This register is used when the device is in test/diagnostic mode.

It is a 24-bit (8 bits each for RED, GREEN and BLUE) wide

read-only register which allows the MPU to read data on the

pixel port, see “Test Diagnostic” section.

MR17

MR16

MR14

MR13

MR12

MR11

MR10

MR15

MR19

MR18

CALIBRATE

LOADIN

MR15

* THESE BITS ARE READ-ONLY RESERVED BITS.

A READ CYCLE WILL RETURN ZEROS "00."

RESERVED*

RAM-DAC

RESOLUTION CONTROL

8-BIT

10-BIT

RESET CONTROL

MR10

MR16

PS0

MR17

PS1

PALETTE SELECT

MATCH BITS CONTROL

MR11

MPU DATA BUS

WIDTH

8-BIT (D7–D0)

10-BIT (D9–D0)

MR12

OPERATIONAL MODE CONTROL

RESERVED

NORMAL OPERATION

RESERVED

MR14 MR13

Mode Register 1 (MR1) (MR19–MR10)

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