ADV7152LS85 datasheet(15/32 Pages) AD

15 / 32 page

ADV7152

–15–

REV. B

PIXEL

INPUT

DATA

ASSIGN-

MENTS

DATA

LATCHED

PIXEL

PORT

DATA

INTERNALLY

SHIFTED

TO 5 LSBS

DATA LATCHES

FIRST 32

LOCATIONS

OF RAM

BLUE

DAC

LOCATION "0"

LOCATION "31"

256 x 10 RAM

(BLUE LUT)

RED

DAC

256 x 10 RAM

(RED LUT)

LOCATION "0"

LOCATION "31"

GREEN

DAC

256 x 10 RAM

(GREEN LUT)

LOCATION "0"

LOCATION "31"

Figure 24. 15-Bit True-Color Mapping Using R0–R7

and G0–G6

MICROPROCESSOR (MPU) PORT

The ADV7152 supports a standard MPU Interface. All the

functions of the part are controlled via this MPU port. Direct

access is gained to the Address Register, Mode Register and all

the Control Registers as well as the Color Palette. The follow-

ing sections describe the setup for reading and writing to all of

the devices registers.

MPU Interface

The MPU interface (Figure 25) consists of a bidirectional,

10-bit wide databus and interface control signals CE, C0, C1

and R/W. The 10-bit wide databus is user configurable as

illustrated.

Table II. Databus Width Table

Databus

RAM/DAC

Read/Write

Width

Resolution

Mode

10 Bit

10-Bit Parallel

10 Bit

8 Bit

8-Bit Parallel

8 Bit

10 Bit

8+2 Byte

8 Bit

8-Bit Parallel

The ADV7152 contains a number of onboard registers includ-

ing the Mode Register (MR17–MR10), Address Register (A7–

A0) and nine Control Registers as well as Red (R9–R0), Green

(G9–G0) and Blue (B9–B0) Color Registers. These registers

control the entire operation of the part. Figure 26 shows the

internal register configuration.

Control lines C1 and C0 determine which register the MPU is

accessing. C1 and C0 also determine whether the Address Reg-

ister is pointing to the color registers and look-up table RAM or

the control registers. If C1, C0 = 1, 0, the MPU has access to

whatever control register is pointed to by the Address Register

(A7–A0). If C1, C0 = 0, 1, the MPU has access to the Look-Up

Table RAM (Color Palette) through the associated color regis-

ters. The CE input latches data to or from the part.

The R/W control input determines between read or write ac-

cesses. The Truth Tables III and IV show all modes of access to

the various registers and color palette for both the 8-bit wide

databus configuration and 10-bit wide databus configuration. It

should be noted that after power-up, the devices MPU port is

automatically set to 10-bit wide operation (see Power-On Reset

section).

Color Palette Accesses

Data is written to the color palette by first writing to the address

performs three successive write cycles for each of the red, green

and blue registers (10 bit or 8 bit). An internal pointer moves

from red to green to blue after each write is completed. This

pointer is reset to red after a blue write or whenever the address

red, green and blue are concatenated into a single 30-bit/24-bit

word and written to the RAM location as specified in the ad-

dress register (A7–A0). The address register then automatically

increments to point to the next RAM location and a similar red,

green and blue palette write sequence is performed. The address

ette RAM location FFH.

MPU PORT

D0 – D9

10 (8+2)

COMMAND

REGISTERS

(CR1–CR3)

(MR1)

DATA TO

PALETTES

CONTROL REGISTERS

COLOR REGISTERS

ADDRESS

MODE

BLUE

R/W

GREEN

RED

PIXEL MASK

TEST

REGISTERS

REVISION

ADDR

(A7–A0)

Figure 25. MPU Port and Register Configuration

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