ADV7152LS85 datasheet(19/32 Pages) AD

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ADV7152

–19–

REV. B

DAC Test Register

(Address Reg (A7–A0) = 01H)

This register is used when the device is in test/diagnostic mode.

It is a 30-bit (10 bits each for RED, GREEN and BLUE) wide

read-only register which allows MPU access to the DAC port,

see “Test Diagnostic” section.

SYNC

, BLANK and IPLL Test Register

(Address Reg (A7–A0) = 02H)

This register is used when the device is in test/diagnostic mode.

It is a 3-bit wide (3 LSBs) read/write register which allows

MPU access to these particular pixel control bits, see “Test

Diagnostic” section.

ID Register

(Address Reg (A7–A0) = 03H)

This is an 8-bit wide “Identification” read-only register. For the

ADV7152 it will always return the hexadecimal value 8CH.

Pixel Mask Register (Address Reg (A7–A0) = 04H)

The contents of the pixel mask register are individually bit-wise

logically AND-ed with the Red, Green and Blue pixel input

stream of data. It is an 8-bit read/write register with D0 corre-

sponding to R0, G0 and B0. For normal operation, this register

is set with FFH.

COMMAND REGISTER 1 (CR1)

(Address Reg (A7–A0) = 05H)

This register contains a number of control bits as shown in the

diagram. CR1 is a 10-bit wide register. However for program-

ming purposes, it may be considered as an 8-bit wide register

(CR18 to CR19 are reserved).

The diagram below shows the various operations under the con-

trol of CR1. This register can be read from as well as written to. In

write mode, “0” should be written to CR11 and CR13–CR17.

In read mode, CR11 and CR13–CR19 are returned as zeros.

COMMAND REGISTER 1 BIT DESCRIPTION

Calibration Control (CR10)

This bit automatically calibrates the onboard LOADIN/

LOADOUT synchronization circuit. MR15 of Mode Register

MR1 must be set to “0.”

SYNCOUT

Control (CR12)

This bit specified whether the video SYNCOUT signal is to be

enabled. On power up a “0” is written to the bit and

“SYNCOUT” is set three-state.

CR12

DISABLE

ENABLE

SYNCOUT

SYNCOUT CONTROL

CR12

CR11

CR10

CALIBRATION CONTROL

CR10

DISABLE

CALIBRATES

ON EVERY

VERTICAL

SYNC

(MR15=0)

CR11

(0)

THIS BIT

SHOULD BE

SET TO ZERO

CR17–CR13

(00000)

THESE BITS

SHOULD BE

SET TO ZERO

CR13

CR14

CR15

CR16

CR17

CR18

CR19

CR18

CR19

CR18

CR19

RESERVED

CR18

CR19

THESE BITS ARE READ-ONLY RESERVED BITS.

A READ CYCLE WILL RETURN ZEROS "00."

Command Register 1 (CR1) (CR19–CR10)

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