ADV7152LS85 datasheet(21/32 Pages) AD

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ADV7152

–21–

REV. B

COMMAND REGISTER 3 (CR3)

(Address Reg (A7–A0) = 07H)

This register contains a number of control bits as shown in the

diagram. CR3 is a 10-bit wide register. However for program-

ming purposes, it may be considered as an 8-bit wide register

(CR38 and CR39 are both reserved).

The diagram shows the various operations under the control of

CR3. This register can be read from as well written to. In read

mode, CR38 and CR39 are both returned as zeros.

COMMAND REGISTER 3-BIT DESCRIPTION

PRGCKOUT Frequency Control (CR31–CR30)

These bits specify the output frequency of the PRGCKOUT

output. PRGCKOUT is a divided down version of the pixel

CLOCK.

BLANK

Pipeline Delay Control (CR35–CR32)

These bits specify the additional pipeline delay that can be

added to the BLANK function, relative to the overall device

pipeline delay (tPD). As the BLANK control normally enters the

video DAC from a shorter pipeline than the video pixel data,

this control is useful in deskewing the pipeline differential.

Pixel Multiplex Control (CR36)

These bits specify the device’s multiplex mode. It, therefore,

also determines the frequency of the LOADOUT signal.

LOADOUT is a divided down version of the pixel CLOCK.

Revision Register

(Address Reg (A7–A0) = 0BH)

This register is a read only register containing the revision of

silicon.

RESERVED*

CR39

CR38

CR37

CR36

CR35

CR34

CR32

CR31

CR30

CR33

* THESE BITS ARE READ-ONLY

RESERVED BITS.

A READ CYCLE WILL RETURN

ZEROS "00".

CR37 CR36

1:1 MUXING: LOADOUT = CLOCK

÷1

2:1 MUXING: LOADOUT = CLOCK

÷2

RESERVED

PIXEL MULTIPLEX CONTROL

tPD

+ 1 x LOADOUT

tPD

+ 2 x LOADOUT

–

tPD

+ 15 x LOADOUT

EXTRA BLANK PIPELINE DELAY CONTROL

(ADDS TO PIXEL PIPELINE DELAY;

tPD)

CR35 CR34 CR33 CR32

BLANK PIPELINE DELAY

–

CR31 CR30

CLOCK

÷4

CLOCK

÷8

CLOCK

÷16

CLOCK

÷32

PRGCKOUT

FREQUENCY CONTROL

Command Register 3 (CR3) (CR39–CR30)

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