REV. 0

ADMCF340

–31–

PWMSYNCWT + 1

PWMSWT (R/W)

15

14

13

12

11

10

987

65432

10

00

0

0

0000

000

00000

DM (0x2061)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

01

0

00

111

00

0

000

00

PWMSYNCWT (R/W)

PWMSYNCWT

DM (0x2060)

15

14

13

12

11

10

9876

543

210

00

0

00

0

0

0

00

00

00

00

PWMDT (R/W)

PWMDT

2

PWMTM

DM (0x2009)

PWMTM (R/W)

PWMTM

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DM (0x2008)

0

0

0

0

0

0

0

0

0

PWMSEG (R/W)

15

14

13

12

11

10

987

6543

210

00000

00

DM (0x200F)

2

PWMTM

SECONDS

CH OUTPUT DISABLE

CL OUTPUT DISABLE

BH OUTPUT DISABLE

BL OUTPUT DISABLE

AH OUTPUT DISABLE

AL OUTPUT DISABLE

0 = ENABLE

1 = DISABLE

A CHANNEL CROSSOVER

B CHANNEL CROSSOVER

C CHANNEL CROSSOVER

0 = NO CROSSOVER

1 = CROSSOVER

Figure 22. Configuration of PWM Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these

bits should always be written as shown.