ADMCF340 datasheet(18/40 Pages) AD

18 / 40 page

REV. 0

ADMCF340

–18–

PWMCHA = PWMCHB

PWMTM

PWMDT

Figure 9. An example of PWM signals suitable for ECM

control. PWMCHA = PWMCHB, BH/BL are a crossover

pair. AL, BH, CH, and CL outputs are disabled. Operation

is in single update mode.

Gate Drive Unit: PWMGATE Register

The gate drive unit of the PWM controller adds features that

simplify the design of isolated gate drive circuits for PWM

inverters. If a transformer-coupled power device gate drive amplifier is

used, the active PWM signal must be chopped at a high frequency.

The PWMGATE Register allows the programming of this high

frequency chopping mode. The chopped active PWM signals

may be required for the high side drivers only, for the low side

drivers only, or for both the high side and low side switches.

Therefore, independent control of this mode for both high side

and low side switches is included with two separate control bits

in the PWMGATE Register.

Typical PWM output signals with high frequency chopping

enabled on both high side and low side signals are shown in

Figure 10. Chopping of the high side PWM outputs (AH, BH,

and CH) is enabled by setting Bit 8 of the PWMGATE Register.

Chopping of the low side PWM outputs (AL, BL, and CL) is

enabled by setting Bit 9 of the PWMGATE Register. The high

chopping frequency is controlled by the 8-bit word (GDCLK)

written to Bits 0 to 7 of the PWMGATE Register. The period

and the frequency of this high frequency carrier are:

GDCLK

CHOP

CLKOUT

=×

()

[]×

×+

()

[]

The GDCLK value may range from 0 to 255, corresponding

to a programmable chopping frequency rate from 19.5 kHz to

5 MHz for a 20 MHz CLKOUT rate. The gate drive features

must be programmed before operation of the PWM controller

and typically are not changed during normal operation of the

PWM controller. Following a reset, by default, all bits of the

PWMGATE Register are cleared so that high frequency

chopping is disabled.

PWMCHA PWMCHA

PWMTM

(GDCLK + 1)

tCK]

PWMTM

PWMDT

Figure 10. Typical PWM signals with high frequency gate

chopping enabled on both high side and low side switches.

(GDCLK is the integer equivalent of the value in Bits 0 to

7 of the PWMGATE Register.)

PWM Polarity Control, PWMPOL Pin

The polarity of the PWM signals produced at the output pins

AH to CL may be selected in hardware by the PWMPOL Pin.

Connecting the PWMPOL Pin to DGND selects active LO PWM

outputs, such that a LO level is interpreted as a command to

turn on the associated power device. Conversely, connecting

the PWMPOL Pin to VDD selects active HI PWM and the asso-

ciated power devices are turned ON by a HI level at the PWM

outputs. There is an internal pull-up on the PWMPOL Pin, so

that if this pin becomes disconnected (or is not connected),

active HI PWM will be produced. The level on the PWMPOL

Pin may be read from Bit 2 of the SYSSTAT Register, where a

zero indicates a measured LO level at the PWMPOL Pin.

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