ADMCF340 datasheet(26/40 Pages) AD

26 / 40 page

REV. 0

ADMCF340

–26–

Also SPORT1 Flag signal (FL1) is externally available through

the FL1/DT1 Pin. This signal is used to drive the external serial

memory input reset.

With SPORT1 configured in UART Mode, the SPORT0 serial

clock (SCLK0) is externally available through the SCLK1/

SCLK0 Pin. The SPORT1 data transmit (DT1) is externally

available through the FL1/DT1 Pin.

SPORT0 Configuration

SPORT0 can be configured in the following modes:

SPORT Mode

UART Mode

SPI Mode

SPORT0 can be configured for UART Mode. In this mode,

the DR0 and RFS0 signals of the internal serial port are

connected together.

DSP

CORE

SPORT1

DT1

FL1

TFS1

RFS1

DR1

SCLK1

DSP

CORE

SPORT0

SCLK0

DT0

DR0

TFS0

RFS0

SPI

CONTROL

BLOCK

MODECTRL REGISTER (04)

SPORT1 BOOT MODE/UART MODE

MODECTRL REGISTER (15)

SPORT0 SPORT MODE/UART MODE

MODECTRL REGISTER (14..13..12)

SPORT0 SPI INTERFACE CONTROL

DT1/FL1

DR1

SCLK1/SCLK0

DT0

DR0

TFS0

RFS0

ADMCF340

Figure 18. SPORT0 and SPORT1 Internal Multiplexing (Simplied Diagram)

SPORT0 can be configured to operate as master SPI interface.

The SPI Mode is set through Bit 14 of MODECTRL Register.

When SPORT0 is configured as SPI interface, the SPORT I/O

pins assume the configuration shown in Table XI.

The Slave Select Pin automatically generates the select signal at

each word transfer. This pin can also be used as a general purpose

I/O during the SPI transfer without affecting the SPORT operations.

The SPI clock polarity and phase are configurable through

Bits 13 and 12 of MODECTRL Register. The SPI transfer using

clock phase is shown in Figure 19 and Figure 20.

ADMCF340 датащи(PDF) 26 Page - Analog Devices

ADMCF340 датащи(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

датащи скачать

ссылки URL