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ADMCF340 датащи(PDF) 29 Page - Analog Devices

номер детали ADMCF340
подробное описание детали  DashDSPTM 64-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End
PDF  40 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADMCF340 датащи(HTML) 29 Page - Analog Devices

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ADMCF340
–29–
Table XIII. DSP Core Registers
Address
Name
Bits
Function
0x3FFA
SPORT0_Rx_Words1
[15 . . . 0]
Multichannel Receive Word Enables
0x3FF9
SPORT0_Rx_Words0
[15 . . . 0]
Multichannel Receive Word Enables
0x3FF8
SPORT0_Tx_Words1
[15 . . . 0]
Multichannel Transmit Word Enables
0x3FF7
SPORT0_Tx_Words0
[15 . . . 0]
Multichannel Transmit Word Enables
0x3FF6
SPORT0_Ctrl_Reg
[15 . . . 0]
Control Register
0x3FF5
SPORT0_Sclkdiv
[15 . . . 0]
Serial Clock Divide Modulus
0x3FF4
SPORT0_Rfsdiv
[15 . . . 0]
Receive Frame Sync Divide Modulus
0x3FF3
SPORT0_Autobuf Ctrl
[15 . . . 0]
Autobuffer Control Register
0x3FF2
SPORT1_Ctrl_Reg
[15 . . . 0]
Control Register
0x3FFF
SYSCNTL
[15 . . . 0]
System Control Register
0x3FFE
MEMWAIT
[15 . . . 0]
Memory Wait State Control Register
0x3FFD
TPERIOD
[15 . . . 0]
Interval Timer Period Register
0x3FFC
TCOUNT
[15 . . . 0]
Interval Timer Count Register
0x3FFB
TSCALE
[7 . . . 0]
Interval Timer Scale Register
0x3FFA . . . F3
Reserved
0x3FF2
SPORT1_CTRL_REG
[15 . . . 0]
SPORT1 Control Register
0x3FF1
SPORT1_SCLKDIV
[15 . . . 0]
SPORT1 Clock Divide Register
0x3FF0
SPORT1_RFSDIV
[15 . . . 0]
SPORT1 Receive Frame Sync Divide
0x3FEF
SPORT1_AUTOBUF_CTRL
[15 . . . 0]
SPORT1 Autobuffer Control Register



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