PCF8523TSSLASH1 datasheet(50/75 Pages) NXP

50 / 75 page

PCF8523

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Product data sheet

Rev. 4 — 5 July 2012

50 of 74

NXP Semiconductors

PCF8523

Real-Time Clock (RTC) and calendar

11. Static characteristics

Table 48.

Static characteristics

VDD = 1.2 V to 5.5 V; VSS =0V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs =40 k; CL = 7 pF; unless otherwise

specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Supplies

VDD

supply voltage

I2C-bus inactive;

for clock data integrity

Tamb = 40 C to +85 C

[1] 1.2-

5.5V

Tamb =+10 C to +85 C

[2] 1.0-

5.5V

I2C-bus active

1.6

5.5

power management function active

1.8

5.5

slew rate

of VDD

0.5

V/ms

VBAT

battery supply voltage

power management function active

1.8

5.5

IDD

supply current

I2C-bus active;

fSCL = 1000 kHz

200

A

I2C-bus inactive (fSCL =0Hz);

interrupts disabled

clock-out disabled;

power management function disabled

(PM[2:0] = 111)

Tamb =25 C;

VDD =3.0 V

[3] -150

-nA

Tamb = 40 C to +85 C;

VDD = 2.0 V to 5.0 V

[3] -

500

clock-out enabled at 32 kHz;

power management function enabled

(PM[2:0] = 000)

Tamb =25 C;

VBAT or VDD =3.0 V

[4] -1200

-nA

Tamb = 40 C to +85 C;

VBAT or VDD = 2.0 V to 5.0 V

[4] -

3600

IL(bat)

battery leakage current

VDD active; VBAT = 3.0 V

100

Power management

Vth(sw)bat battery switch threshold

voltage

2.28

2.5

2.7

Inputs[5]

VIL

LOW-level input voltage

0.3VDD

VIH

HIGH-level input

voltage

0.7VDD

input voltage

0.5

VDD +0.5 V

ILI

input leakage current

VI = VSS or VDD

-0

-nA

post ESD event

1-

A

input capacitance

[6] --

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