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ADM1024ARU датащи(PDF) 3 Page - Analog Devices |
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ADM1024ARU датащи(HTML) 3 Page - Analog Devices |
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3 / 28 page ![]() –3– REV. 0 ADM1024 Parameter Min Typ Max Unit Test Conditions/Comments SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH 2.2 V Input Low Voltage, VIL 0.8 V Hysteresis 500 mV Glitch Immunity 100 ns DIGITAL INPUT LOGIC LEVELS (See Note 7) (ADD, CI, RESET, VID0–VID4, FAN1, FAN2) Input High Voltage, VIH 2.2 V VCC = 2.85 V – 5.5 V Input Low Voltage, VIL 0.8 V VCC = 2.85 V – 5.5 V NTEST_IN Input High Voltage, VIH 2.2 V VCC = 2.85 V – 5.5 V DIGITAL INPUT CURRENT Input High Current, IIH –1 µAV IN = VCC Input Low Current, IIL 1 µAVIN = 0 Input Capacitance, CIN 20 pF SERIAL BUS TIMING 8 Clock Frequency, fSCLK 400 kHz See Figure 1 Glitch Immunity, tSW 50 ns See Figure 1 Bus Free Time, tBUF 1.3 µs See Figure 1 Start Setup Time, tSU;STA 600 ns See Figure 1 Start Hold Time, tHD;STA 600 ns See Figure 1 SCL Low Time, tLOW 1.3 µs See Figure 1 SCL High Time, tHIGH 0.6 µs See Figure 1 SCL, SDA Rise Time, tr 300 ns See Figure 1 SCL, SDA Fall Time, tf 300 µs See Figure 1 Data Setup Time, tSU;DAT 100 ns See Figure 1 Data Hold Time, tHD;DAT 900 ns See Figure 1 NOTES 1All voltages are measured with respect to GND, unless otherwise specified. 2Typicals are at T A = 25 °C and represent most likely parametric norm. Shutdown current typ is measured with V CC = 3.3 V. 3TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC, multiplexer and on-chip input attenuators, including an external series input protection resistor value between zero and 1 k Ω. 4Total monitoring cycle time is nominally m × 755 µs + n × 33244 µs, where m is the number of channels configured as analog inputs, plus two for the internal V CC measurement and internal temperature sensor, and n is the number of channels configured as external temperature channels (D1 and D2). 5The total fan count is based on two pulses per revolution of the fan tachometer output. 6Open-drain digital outputs may have an external pull-up resistor connected to a voltage lower or higher than V CC (up to 6.5 V absolute maximum). 7All logic inputs except ADD are tolerant of 5 V logic levels, even if V CC is less than 5 V. ADD is a three-state input that may connected to VCC, GND, or left open-circuit. 8Timing specifications are tested at logic levels of V IL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge. Specifications subject to change without notice. P S P tHD;STA tSU;STA tSU;DAT tHIGH tF tHD;DAT tR tLOW tHD;STA tBUF S SCL SDA tSU;STO Figure 1. Diagram for Serial Bus Timing |
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