ADM1024ARU datasheet(20/28 Pages) AD

20 / 28 page

ADM1024

–20–

REV. 0

THERM is cleared by reading the status register, it will be

reasserted after the next temperature reading and comparison if

it remains above the high limit.

THERM is cleared by setting Bit 6 of Conﬁguration Register

1, it cannot be reasserted until this bit is cleared.

THERM will also be asserted if one of the hardware temperature

limits at addresses 13h, 14h, 17h, or 18h is exceeded for three

consecutive measurements. When this happens, the analog output

will be forced to FFh to boost a controlled cooling fan to full speed.

Reading Status Register 1 will not clear

THERM in this case,

because errors caused by exceeding the hardware temperature

limits are stored in a separate register that is not cleared by

reading the status register. In this case,

THERM can only be

cleared by setting Bit 0 of Conﬁguration Register 2.

THERM will be cleared automatically if the temperature falls at

least 5 degrees below the limit for three consecutive measurements.

ACPI MODE

In ACPI mode,

THERM responds only to the hardware tem-

perature limits at addresses 13h, 14h, 17h and 18h, not to the

software programmed limits.

HARDWARE

TRIP POINT

THERM

ANALOG

OUTPUT

TEMP

PROGRAMMED

VALUE

FFh

EXT

THERM

INPUT

Figure 23b.

THERM Output in ACPI Mode

THERM will go low if either the internal or external hardware

temperature limit is exceeded for three consecutive measurements.

It will remain low until the temperature falls at least 5 degrees

below the limit for three consecutive measurements. While

THERM is low, the analog output will go to FFh to boost a

controlled fan to full speed.

RESET INPUT/OUTPUT

RESET (Pin 12) is an I/O pin that can function as an open-

drain output, providing a low-going 20 ms output pulse when

Bit 4 of the Conﬁguration Register is set to 1, provided the reset

function has ﬁrst been enabled by setting Bit 7 of Interrupt

Mask Registers #2 to 1. The bit is automatically cleared when

the reset pulse is output. Pin 11 can also function as a

RESET

input by pulling this pin low to reset the internal registers of the

ADM1024 to default values. Only those registers that have power

on default values as listed in Table VI are affected by this function.

The DAC register, Value and Limit Registers are not affected.

NAND TESTS

A NAND gate is provided in the ADM1024 for Automated Test

Equipment (ATE) board level connectivity testing. The device

is placed into NAND Test Mode by powering up with Pin 11 held

high. This pin is automatically sampled after power-up and if it

is connected high, then the NAND test mode is invoked.

In NAND test mode, all digital inputs may be tested as illustrated

below. NTEST_OUT/ADD will become the NAND test output

pin. To perform a NAND tree test all pins included in the NAND

tree should ﬁrst be driven high. Each pin can then be toggled

and a resulting toggle can be observed on NTEST_OUT/ADD.

Allow for a typical propagation delay of 500 ns. The structure of

the NAND tree is shown in Figure 24.

LATCH

ENABLE

POWER-ON

RESET

NTEST IN/AOUT

SDA

SCL

FAN1

FAN2

VID0

VID1

VID2

VID3

VID4

NTEST OUT/ADD

Figure 24. NAND Tree

Note that NTEST_OUT/ADD is a dual function line and if

both functions are required, then this line should not be hard-

wired directly to VCC/GND. Instead it should be connected via a

5 k

Ω resistor.

Note: If any of the inputs shown in Figure 24 are unused, they

should not be connected directly to ground, but via a resistor such

as 10 k

Ω. This will allow the ATE (Automatic Test Equipment)

to drive every input high so that the NAND tree test can be carried

out properly.

USING THE ADM1024

POWER-ON RESET

When power is ﬁrst applied, the ADM1024 performs a “power-

on reset” on several of its registers. Registers whose power-on

values are not shown have power-on conditions that are indeter-

minate (this includes the Value and Limit Registers). The ADC

is inactive. In most applications, usually the ﬁrst action after

power-on would be to write limits into the Limit Registers.

Power-on reset clears or initializes the following registers (the ini-

tialized values are shown in Table VIII):

• Conﬁguration Registers #1 and #2

• Channel Mode Register

• Interrupt (

INT) Status Registers #1 and #2

• Interrupt (

INT) Status Mirror Registers #1 and #2

• Interrupt (

INT) Mask Registers #1 and #2

• VID/Fan Divisor Register

• VID4 Register

• Chassis Intrusion Clear Register

• Test Register

• Analog Output Register

• Hardware Trip Registers

INITIALIZATION

Conﬁguration Register INITIALIZATION performs a similar,

but not identical, function to power-on reset. The Test Register

and Analog Output Register are not initialized.

Conﬁguration Register INITIALIZATION is accomplished by

setting Bit 7 of the Conﬁguration Register high. This bit auto-

matically clears after being set.

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