AD9773AST datasheet(15/19 Pages) AD

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AD9773

PRELIMINARY TECHNICAL DATA

PROGRAMMABLE MODES

The AD9773 has a very flexible structure, program-

mable via the SPI compliant port with registers defined

in table 1. Digital filtering and complex modulation can

be programmed, as well as fine and coarse adjustments

for the I and Q DAC channels.

PLL ENABLED

With the Phase Locked Loop (PLL) enabled, a single

ended or differential clock, running at the input data

rate, must be applied to the CLK+/CLK- inputs. If a

single ended clock is to be used, both of these inputs

should have the same dc bias. Data at the input ports

one and two is latched into the AD9773 on the rising

edge of the input clock. Care should be taken to ensure

that the transitions of the input data do not violate the

specified set-up and hold times.

The PLL clock multiplier and distribution circuitry

produces the necessary internal synchronized 1

×,2×, 4×,

and 8

× clocks for the rising edge triggered latches, in-

terpolation filters, modulators and DACs. Figure 7

shows a functional block diagram of the AD9773 clock

circuitry with the PLL enabled.This circuitry consists

of a phase detector, charge pump, voltage controlled

oscillator (VCO), prescaler, clock distribution and SPI

port control.The charge pump andVCO are powered

from PLLVDD while the differential clock input buffer,

phase detector, prescaler and clock distribution are

powered from CLKVDD. PLL lock status is indicated

by the logic signal at the PLL_LOCK pin.To ensure

optimum phase noise performance from the PLL clock

multiplier and clock distribution, PLLVDD and

CLKVDD must originate from the same clean analog

supply.

The speed of theVCO with the PLL enabled also has

an effect on phase noise. Optimal phase noise with re-

spect toVCO speed is achieved by running theVCO in

the range of 500MHz to 550MHz.TheVCO speed is a

function of the input data rate, of the interpolation rate

and of theVCO prescaler according to the following

function;

Figure 7. AD9773 PLL and Clock Circuitry with PLL Enabled

Figure 8. AD9773 PLL and Clock Circuitry with PLL Disabled

VCO Speed (MHz) =

Input Data Rate (MHz)

× Interpolation Rate × Prescaler

It is important to note that the resistor/capacitor needed

for the PLL loop filter is included on the AD9773.This

will suffice unless the input data rate is below 10MHz,

in which case an external series RC will need to be

added between the LPF and PLLVDD pins.

PLL DISABLED,TWO PORT MODE

With the PLL disabled, and the AD9773 in two port

mode, a single ended or differential clock, running at

the DAC output rate, must be applied to the CLK+/

CLK- inputs. In this mode, the internal clock dividers

on the AD9773 are used to create a clock, available at

the DATACLK pin, which runs at the input data rate.

This can be used synchronize the input data. Figure 8

shows a functional block diagram of the AD9773 clock

circuitry with the PLL disabled.

The two port mode is selected by setting control

ports one and two of the AD9773 on the rising edge of

the clock at the DATACLK/PLL_LOCK pin (pin 8).

This clock can be internally generated by the AD9773

or externally applied by setting control register 02h, bit

3 to the desired value.Whether externally or internally

generated, the speed of this clock is defined by the

speed of the clock at CLK+/CLK-, divided by the

PRESCALER

CHARGE

PUMP

PHASE

DETECTOR

CLK+

CLOCK

DISTRIBUTION

CIRCUITRY

VCO

AD9773

CLK-

SP I P ORT

INTERNAL SP I

CONTROL

REGISTERS

DATACLK

INTERP OLATION

FILTERS,

MODULATORS

AND DACS

× 4×

INTERP OLATION

RATE

CONTROL

P LL DIVIDER

(P RESCALER)

CONTROL

PLL

CONTROL

(P LL OFF)

INP UT

DATA

LATCHES

MODULATION

RATE

CONTROL

PRESCALER

CHARGE

PUMP

PHASE

DETECTOR

CLK+

CLOCK

DISTRIB UTION

CIRCUITRY

VCO

AD9773

CLK-

SP I P ORT

INTERNAL SP I

CONTROL

REGISTERS

P LL_LOCK

1=LOCK

0=NO LOCK

P LLVDD

LP F

INTERP OLATION

FILTERS,

MODULATORS

AND DACS

× 4×

INTERP OLATION

RATE

CONTROL

P LL DIVIDER

(P RESCALER)

CONTROL

PLL

CONTROL

(P LL ON)

INP UT

DATA

LATCHES

MODULATION

RATE

CONTROL

REV. PrA

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