AD9773AST datasheet(14/19 Pages) AD

14 / 19 page

AD9773

PRELIMINARY TECHNICAL DATA

format. That is, if the AD9773 is in LSB first mode, the

instruction byte must be written from least significant bit

to most significant bit. Multibyte data transfers in MSB

format can be completed by writing an instruction byte

that includes the register address of the most significant

byte. In MSB first mode, the serial port internal byte

address generator decrements for each byte required of

the multibyte communication cycle. Multibyte data trans-

fers in LSB first format can be completed by writing an

instruction byte that includes the register address of the

least significant byte. In LSB first mode, the serial port

internal byte address generator increments for each byte

required of the multibyte communication cycle.

The AD9773 serial port controller address will incre-

ment from 1Fh to 00h for multibyte I/O operations if the

MSB first mode is active. The serial port controller

address will decrement from 00h to 1Fh for multibyte I/

O operations if the LSB first mode is active.

Notes on Serial Port Operation

The AD9773 serial port configuration bits reside in bits

6 and 7 of register address 00h. It is important to note that

the configuration changes immediately upon writing to the

last bit of the register. For multibyte transfers, writing to

this register may occur during the middle of communi-

cation cycle. Care must be taken to compensate for this

new configuration for the remaining bytes of the current

communication cycle.

The same considerations apply to setting the reset bit in

default values but the software reset doesn’t affect the bits

in register address 00h.

It is recommended to use only single byte transfers when

changing serial port configurations or initiating a soft-

ware reset.

A write to bits 1, 2 and 3 of address 00h with the same

logic levels as for bits 7, 6 and 5 (bit pattern: XY1001YX

binary) allows to reprogram a lost serial port configura-

tion and to reset the registers to their default values. A

second write to address 00h with Reset bit low and serial

port configuration as specified above (XY) reprograms

the OSC IN Multiplier setting. A changed fSYSCLK fre-

quency is stable after a maximum of 200 fMCLK cycles

(=Wake-Up Time).

R/W I6 (n) I5 (n)

D7n

D6n

D20 D10

D00

D7n

D6n

D20 D10

D00

Instruction Cycle

Data Transfer Cycle

SCLK

SDIO

SDO

R/W

I6 (n)

I5 (n)

D7n

D6n

D20

D10

D00

D7n

D6n

D20

D10

D00

Instruction Cycle

Data Transfer Cycle

SCLK

SDIO

SDO

Figure 4a. Serial Register Interface Timing MSB-First

Figure 4b. Serial Register Interface Timing LSB-First

Figure 5. Timing Diagram for Register Write to AD9773

tDS

tSCLK

tDH

tPW H

tPW L

Instruc tion Bit

Instructio n Bit 6

SCLK

SDIO

tDV

SCLK

SDIO

SDO

Data Bit n

Data Bit n-1

Figure 6. Timing Diagram for Register Read from AD9773

REV. PrA

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