AD9773

11

PRELIMINARY TECHNICAL DATA

Register Description

Address 00h Bit 7

Logic 0 (default), causes the SDIO pin to act as an input during the data transfer (phase 2) of

the communications cycle. When set to a 1, SDIO can act as an input or output, depending on

bit 7 of the instruction byte.

Bit 6

Logic 0 (default). Determines the direction (LSB/MSB first) of the communications and data

transfer communications cycles. Refer to the section MSB/LSB Transfers on page 9 for a

detailed description.

Bit 5

Writing a one to this bit resets the registers to their default values and restarts the chip. The

RESET bit always reads back 0. Register address 0h bits are not cleared by this software reset.

However, a high level at the RESET pin forces all registers, including those in address 0h, to

their default state.

Bit 4

A logic 1 to this bit shuts down the DAC output currents.

Bit 3

Powerdown. Logic 1 shuts down all analog and digital functions.

Bit 2

1R/2R Mode. The default (0) places the AD9773 in 2 resistor mode. In this mode, the I

REF

currents for the I and the Q DAC references are set separately by FSADJ1 and FSADJ2 on

pins 60 and 59. In this case, I

bit set to 1, the reference currents for both I and Q DACs are controlled by a single resistor on

pin 60. I

Bit 1

PLL_LOCK indicator. When the PLL is enabled, reading this bit will give the status of the

PLL. A logic 1 indicates the PLL is locked. A logic 0 indicates an unlocked state.

Address 01h Bit 7,6

Filter interpolation rate according to the following table:

00

1

×

01

2

×

10

4

×

11

8

×

Bit 5,4

Modulation mode according to the following table:

00

none

01

fs/2

10

fs/4

11

fs/8

Address 01h Bit 3

Logic 1 enables zero stuffing mode for interpolation filters

Bit 2

Default(1) enables the real mix mode. The I and Q data channels are individually modulated

by Fs/2,Fs/4 or Fs/8 after the interpolation filters. However, no complex modulation is done.

In the complex mix mode (logic 0), the digital modulators on the I and Q data channels are

coupled to create a digital complex modulator.When the AD9773 is applied in conjunction

with an external quadrature modulator, rejection can be achieved of either the higher or lower

frequency image around the 2nd IF frequency (i.e., the 2nd IF frequency is the LO of

the analog quadrature modulator external to the AD9773) according to the bit value of

register 01h, bit 1.

Bit 1

rejection of the higher frequency image when the AD9773 is used with an external quadrature

the lower frequency image

Address 02h Bit 7

Logic 0 (default) causes data to be accepted on the inputs as 2’s complement binary. Logic 1

causes data to be accepted as straight binary.

Bit 6

Logic 0 (default) places the AD9773 in two port mode. I and Q data enters the AD9773 via

ports one and two, respectively. A logic 1 places the AD9773 in one port mode in which

interleaved I and Q data is applied to port one. See pin function descriptions for DATACLK/

PLL_LOCK, IQSEL and ONEPORTCLK for detailed information on how to use these

modes.

Bit 5

DATACLK driver strength. With the internal PLL disabled, and this bit set to logic 0, it is

recommended that DATACLK be buffered. When this bit is set to logic 1, DATACLK acts as

a stronger driver capable of driving small capacitive loads.

Bit 3

External dataclock. With the PLL disabled, pin 8 (DATACLK/PLL_LOCK) becomes a data

clock which must run at the same rate as the input data.If this bit is set to a 0 (default), pin 8 is

an output and theAD9773 creates this clock. If this bit is a logic 1, pin 8 is an input and an

external data clock must be applied and sychronized with the higher rate clock driving CLK+

and CLK-.

REV. PrA