AD9773–SPECIFICATIONS

7

PRELIMINARY TECHNICAL DATA

PIN FUNCTION DESCRIPTIONS

Pin No.

Name

73,72

I

OUTA1

, I

OUTB1

Differential DAC current outputs, I Channel

69,68

I

OUTA2

, I

OUTB2

Differential DAC current outputs, Q Channel

58

REFIO

Reference output, 1.2V nominal

60

FSADJ1

Full-scale current adjust, I channel

59

FSADJ2

Full-scale current adjust, Q channel

5

CLK+

Differential Clock input

6

CLK-

Differential Clock input

8

DATACLK/PLL_LOCK

With the PLL enabled, this pin indicates the state of the PLL. A

read of a logic 1 indicates the PLL is in the locked state. Logic

0 indicates the PLL has not achieved lock. With the PLL dis-

abled, and the AD9773 in two port mode, this pin becomes a

clock signal, running at the input data rate, which may either be

input to the AD9773, or generated by the AD9773, depending

on the state of address 2h, bit 3 in the SPI control register.

2

LPF

PLL Loop Filter

57

RESET

Logic one resets all of the SPI port registers, including address

0h, to their default values. A software reset can also be done

by writing a logic one to SPI register 0h, bit 5. However, the

software reset has no effect on the bits in address 0h.

11-16,19-24

P1B11 to P1B0

Port 1 data inputs

31

IQSEL/P2B15

In one port mode, IQSEL = 1 followed by a rising edge of the

differential input clock will latch the data into the I channel

input register. IQSEL = 0 will latch the data into the Q

channel input register. In two port mode, this pin becomes the

port 2 MSB.

32

ONEPORTCLK/P2B14

With the PLL disabled, and the AD9773 in one port mode, this

pin becomes a clock output which runs at twice the input data

rate of the I and Q channels.This allows the AD9773 to accept

and demux interleaved I and Q data to the I and Q input reg-

isters.

33,34,37-42,45,46

P2B11 to P2B0

Port 2 data inputs.

56

SPI_CSB

Chip select/SPI data synchronization. On momentary logic

high, resets SPI port logic and initializes instruction cycle.

55

SPI_CLK

Data input to the SPI port is registered on the rising edge of

SPI_CLK. Data output on the SPI port is registered on the

falling edge.

54

SPI_SDIO

Bidirectional data pin. Data direction is controlled by bit 7 of

register address 0h.The default setting for this bit is 0, which

sets SDIO as an input.

53

SPI_SDO

In the case where SDIO is an input, SDO acts as an output.

When SDIO becomes an output, SDO enters a high Z state.

79,77,75,74,71,70,

67,66,64,62

ACOM

Analog Common

80.78.76,65,63,61

AVDD

Analog SupplyVoltage

51,43,36,26,17,10

DVDD

Digital SupplyVoltage

52,44,35,25,18,9

DCOM

Digital Common

1,3

CLKVDD

Clock SupplyVoltage

4,7

CLKCOM

Clock Supply Common

REV. PrA