AD9773

12

PRELIMINARY TECHNICAL DATA

Address 03h Bit 1,0

Setting this divide ratio to a higher number allows the VCO in the PLL to run at a high rate (for

best performance) while the DAC input and output clocks run substantially slower. The

divider ratio is set according to the following table:

00

÷1

01

÷2

10

÷4

11

÷8

Address 04h Bit 7

Logic 0 (default) disables the internal PLL. Logic 1 enables the PLL.

Bit 6

Logic 0 (default) sets the charge pump control to automatic. In this mode, the charge pump

bias current is controlled by the divider ratio defined in address 3h, bits 1 and 0. Logic 1

allows the user to manually define the charge pump bias current using address 4h, bits 2, 1

and 0. Adjusting the charge pump bias current allows the user to optimize the noise/settling

performance of the PLL.

Bit 2,1,0

With the charge pump control set to manual, these bits define the charge pump bias current

according to the following table:

000

50

µamps

001

100

010

200

011

400

100

800

Address 05h,09h

Bits 7-0 These bits represent an 8 bit binary number (bit 7, MSB) which defines the fine gain

adjustment of the I (5h) and Q (9h) DAC according to the equation given below.

Address 06h,0Ah

Bits 3-0 These bits represent a 4 bit binary number (bit 3, MSB) which defines the coarse

gain adjustment of the I (6h) and Q (Ah) DACs according to the equation below.

Address 07h,0Bh

Bits 7-0

Address 08h,0Ch

Bit 1,0

The ten bits from these two address pairs (7h,8h and Bh,Ch) represent a 10 bit

binary number which defines the offset adjustment of the I and Q DACs according to

the equation below (7h,Bh - bit 7 MSB / 8h,Ch - bit 0 LSB)

Address 08h,0Ch

Bit 7

This bit determines the direction of the offset of the I (8h) and Q (Ch) DACs. A logic

0 will apply a positive offset current to I

offset current to I

addresses 7h,Bh,8h,Ch according the the formulas given below.

Figure 2. I

*Note that I

description for 1R/2R mode control on page 11 (address 0h, bit 2) for the value I

either mode.





































×



































 ×

−













+











 ×

=

16

REF

REF

OUTA

2

data

24

1024

256

fine

32

I

3

16

1

coarse

8

I

6

I

































×



































 ×

−













+











 ×

=

16

16

REF

REF

OUTB

2

1

-

data

-

2

24

1024

256

fine

32

I

3

16

1

coarse

8

I

6

I

(1R Mode)

(2R Mode)













×

=

1024

OFFSET

I

4

I

REF

OFFSET













×

=

1024

OFFSET

I

2

I

REF

OFFSET

REV. PrA