AD9772EB datasheet(24/32 Pages) AD

24 / 32 page

REV. A

AD9772A

–24–

AOUT – dBFS

–14

–12

–10

–8

–6

–2

–4

325MHz

275MHz

75MHz

125MHz

Figure 35. Dual-Tone “Windowed” SFDR vs. AOUT @

fDATA = 100 MSPS

For many applications, the data update rate to the DAC (i.e.,

fDATA) must be some fixed integer multiple of some system

reference clock (i.e., GSM – 13 MHz). Furthermore, these

applications prefer to use standard IF frequencies which offer

a large selection of SAW filter choices of varying passbands

(i.e., 70 MHz). These applications may still benefit from the

AD9772A’s direct IF mode capabilities when used in conjunc-

tion with a digital upconverter such as the AD6622. Since the

AD6622 can digitally synthesize and tune up to four modulated

carriers, it is possible to judiciously tune these carriers in a region

which may fall within an IF filter’s passband upon reconstruc-

tion by the AD9772A. Figure 36 shows an example in which

four carriers were tuned around 18 MHz with a digital upcon-

verter operating at 52 MSPS such that when reconstructed by

the AD9772A in the IF MODE, these carriers fall around a

70 MHz IF.

FREQUENCY – MHz

–10

–110

–30

–50

–70

–90

–80

–60

–40

–20

Figure 36. Spectral Plot of Four Carriers at 60 MHz IF

with fDATA = 52 MSPS, PLLVDD = 0

AD9772A EVALUATION BOARD

The AD9772-EB is an evaluation board for the AD9772A TxDAC.

Careful attention to layout and circuit design, combined with

prototyping area, allows the user to easily and effectively evalu-

ate the AD9772A in different modes of operation.

Referring to Figures 37 and 38, the AD9772A’s performance

can be evaluated differentially or single-endedly using a trans-

former, differential amplifier, or directly coupled output. To

evaluate the output differentially using the transformer, remove

jumpers JP12 and JP13 and monitor the output at J6 (IOUT).

To evaluate the output differentially, remove the transformer

(T2) and install jumpers JP12 and JP13. The output of the

amplifier can be evaluated at J13 (AMPOUT). To evaluate the

AD9772A single-endedly and directly coupled, remove the

transformer and jumpers (JP12 and JP13) and install resistors

R16 or R17 with 0

Ω.

The digital data to the AD9772A comes across a ribbon cable

which interfaces to a 40-pin IDC connector. Proper termination

or voltage scaling can be accomplished by installing RN2 and/or

RN3 SIP resistor networks. The 22

Ω DIP resistor network,

RN1, must be installed and helps reduce the digital data edge

rates. A single-ended CLOCK input can be supplied via the

ribbon cable by installing JP8 or more preferably via the SMA

connector, J3 (CLOCK). If the CLOCK is supplied by J3, the

AD9772A can be configured for a differential clock interface by

installing jumpers JP1 and configuring JP2, JP3, and JP9 for the

DF position. To configure the AD9772A clock input for a single-

ended clock interface, remove JP1 and configure JP2, JP3 and

JP9 for the SE position.

The AD9772A’s PLL clock multiplier can be disabled by con-

figuring jumper JP5 for the L position. In this case, the user

must supply a clock input at twice (2 ) the data rate via J3

(CLOCK). The 1

clock is made available on SMA con-

nector J1 (PLLLOCK), and should be used to trigger a pattern

generator directly or via a programmable pulse generator. Note

that PLLLOCK is capable of providing a 0 V to 0.85 V output

into a 50

Ω load. To enable the PLL clock multiplier, JP5 must

be configured for the H position. In this case, the clock may be

supplied via the ribbon cable (i.e., JP8 installed) or J3 (CLOCK).

The divide-by-N ratio can be set by configuring JP6 (DIV0) and

JP7 (DIV1).

The AD9772A can be configured for Baseband or Direct IF Mode

operation by configuring jumpers JP11 (MOD0) and JP10

(MOD1). For baseband operation, JP10 and JP11 should be

configured in the L position. For direct IF operation, JP10 and

JP11 should be configured in the H position. For direct IF

operation without “zero-stuffing,” JP11 should be configured in

the H position while JP10 should be configured in the low position.

The AD9772A’s voltage reference can be enabled or disabled

via JP4 (EXT REF IN). To enable the reference, configure JP in

the INT position. A voltage of approximately 1.2 V will appear

at the TP6 (REFIO) test point. To disable the internal refer-

ence, configure JP4 in the EXT position and drive TP6 with an

external voltage reference. Lastly, the AD9772A can be placed

in the SLEEP mode by driving the TP11 test point with logic

level HIGH input signal.

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