AD9772EB datasheet(4/32 Pages) AD

номер детали	AD9772EB

подробное описание детали	14-Bit, 160 MSPS TxDAC with 2x Interpolation Filter

PDF	32 Pages

Scroll/Zoom	100%

производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

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4 / 32 page

REV. A

–4–

AD9772A–SPECIFICATIONS

DIGITAL SPECIFICATIONS

Parameter

Min

Typ

Max

Unit

DIGITAL INPUTS

Logic “1” Voltage

2.1

Logic “0” Voltage

0.9

Logic “1” Current*

–10

+10

µA

Logic “0” Current

–10

+10

µA

Input Capacitance

CLOCK INPUTS

Input Voltage Range

Common-Mode Voltage

0.75

1.5

2.25

Differential Voltage

0.5

1.5

PLL CLOCK ENABLED—FIGURE 1a

Input Setup Time (tS), TA = 25

°C

0.5

Input Hold Time (tH), TA = 25

°C

1.0

Latch Pulsewidth (tLPW), TA = 25

°C

1.5

PLL CLOCK DISABLED—FIGURE 1b

Input Setup Time (tS), TA = 25

°C

–1.2

Input Hold Time (tH), TA = 25

°C

3.2

Latch Pulsewidth (tLPW), TA = 25

°C

1.5

CLK/PLLLOCK Delay (tOD), TA = 25

°C

2.8

3.2

PLLLOCK (VOH), TA = 25

°C

3.0

PLLLOCK (VOL), TA = 25

°C

0.3

*MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15

µA.

Specifications subject to change without notice.

(TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless

otherwise noted.)

0.025%

DB0–DB13

CLK+ – CLK–

IOUTA

IOUTB

tLPW

tPD

tST

Figure 1a. Timing Diagram—PLL Clock Multiplier Enabled

DB0–DB13

0.025%

IOUTA

IOUTB

tOD

PLLLOCK

CLK+ – CLK–

tLPW

tPD

tST

Figure 1b. Timing Diagram—PLL Clock Multiplier Disabled

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