AD9772EB datasheet(18/32 Pages) AD

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REV. A

AD9772A

–18–

Operating the AD9772A with reduced voltage output swings at

IOUTA and IOUTB in a differential or single-ended output configu-

ration reduces the signal dependency of its output impedance,

thus enhancing distortion performance. Although the voltage

compliance range of IOUTA and IOUTB extends from –1.0 V to

+1.25 V, optimum distortion performance is achieved when the

maximum full-scale signal at IOUTA and IOUTB does not exceed

approximately 0.5 V. A properly selected transformer with a

grounded center-tap will allow the AD9772A to provide the

required power and voltage levels to different loads while main-

taining reduced voltage swings at IOUTA and IOUTB. DC-coupled

applications requiring a differential or single-ended output con-

figuration should size RLOAD accordingly. Refer to Applying the

AD9772A section for examples of various output configurations.

The most significant improvement in the AD9772A’s distortion

and noise performance is realized using a differential output

configuration. The common-mode error sources of both IOUTA and

IOUTB can be substantially reduced by the common-mode rejection

of a transformer or differential amplifier. These common-

mode error sources include even-order distortion products

and noise. The enhancement in distortion performance becomes

more significant as the reconstructed waveform’s frequency

content increases and/or its amplitude decreases. The distor-

tion and noise performance of the AD9772A is also dependent

on the full-scale current setting, IOUTFS. Although IOUTFS can be

set between 2 mA and 20 mA, selecting an IOUTFS of 20 mA will

provide the best distortion and noise performance.

In summary, the AD9772A achieves the optimum distortion

and noise performance under the following conditions:

1. Positive voltage swing at IOUTA and IOUTB limited to 0.5 V.

2. Differential Operation.

3. IOUTFS set to 20 mA.

4. PLL Clock Multiplier Disabled

Note the majority of the AC Characterization Curves for the

AD9772A are performed under the above-mentioned operating

conditions.

DIGITAL INPUTS/OUTPUTS

The AD9772A consists of several digital input pins used for

data, clock, and control purposes. It also contains a single digi-

tal output pin, PLLLOCK, used to monitor the status of the

internal PLL clock multiplier or provide a 1 clock output. The

14-bit parallel data inputs follow standard positive binary coding

where DB13 is the most significant bit (MSB), and DB0 is the

least significant bit (LSB). IOUTA produces a full-scale output

current when all data bits are at Logic 1. IOUTB produces a

complementary output with the full-scale current split between

the two outputs as a function of the input code.

The digital interface is implemented using an edge-triggered

master slave latch and is designed to support an input data rate

as high as 160 MSPS. The clock can be operated at any duty

cycle that meets the specified latch pulsewidth as shown in

Figures 1a and 1b. The setup and hold times can also be varied

within the clock cycle as long as the specified minimum times

are met. The digital inputs (excluding CLK+ and CLK–) are

CMOS-compatible with its logic thresholds, VTHRESHOLD, set to

approximately half the digital positive supply (i.e., DVDD or

CLKVDD) or

VTHRESHOLD = DVDD/2 (

±20%)

The internal digital circuitry of the AD9772A is capable of operat-

ing over a digital supply range of 2.8 V to 3.2 V. As a result, the

digital inputs can also accommodate TTL levels when DVDD is

set to accommodate the maximum high level voltage of the TTL

drivers VOH(MAX). Although a DVDD of 3.3 V will typically ensure

proper compatibility with most TTL logic families, a series

200

Ω resistors are recommended between the TTL logic driver

and digital inputs to limit the peak current through the ESD pro-

tection diodes if VOH(MAX) exceeds DVDD by more than 300 mV.

Figure 19 shows the equivalent digital input circuit for the data

and control inputs.

DIGITAL

INPUT

DVDD

Figure 19. Equivalent Digital Input

The AD9772A features a flexible differential clock input oper-

ating from separate supplies (i.e., CLKVDD, CLKCOM) to

achieve optimum jitter performance. The two clock inputs,

CLK+ and CLK–, can be driven from a single-ended or differen-

tial clock source. For single-ended operation, CLK+ should be

driven by a single-ended logic source while CLK– should be set

to the logic source’s threshold voltage via a resistor divider/capaci-

tor network referenced to CLKVDD as shown in Figure 20. For

differential operation, both CLK+ and CLK– should be biased to

CLKVDD/2 via a resistor divider network as shown in Figure 21.

An RF transformer as shown in Figure 3 can also be used to

convert a single-ended clock input to a differential clock input.

RSERIES

VTHRESHOLD

AD9772A

CLK+

CLKVDD

CLK–

CLKCOM

0.1 F

Figure 20. Single-Ended Clock Interface

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