PCAL9535APW datasheet(11/46 Pages) NXP

11 / 46 page

PCAL9535A

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Product data sheet

Rev. 1 — 28 September 2012

11 of 46

NXP Semiconductors

PCAL9535A

Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O

6.2.9 Pull-up/pull-down selection register pair (48h, 49h)

The I/O port can be configured to have a pull-up or pull-down resistor by programming the

pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k

 pull-up

resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k

 pull-down resistor for that

I/O pin. If the pull-up/pull-down feature is disconnected, writing to this register will have no

effect on I/O pin. Typical value is 100 k

 with minimum of 50 k and maximum of 150 k.

A register pair write is described in Section 7.1 and a register pair read is described in

Section 7.2.

6.2.10 Interrupt mask register pair (4Ah, 4Bh)

Interrupt mask registers are set to logic 1 upon power-on, disabling interrupts during

system start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0.

If an input changes state and the corresponding bit in the Interrupt mask register is set

to 1, the interrupt is masked and the interrupt pin will not be asserted. If the corresponding

bit in the Interrupt mask register is set to 0, the interrupt pin will be asserted.

When an input changes state and the resulting interrupt is masked (interrupt mask bit

is 1), setting the input mask register bit to 0 will cause the interrupt pin to be asserted.

If the interrupt mask bit of an input that is currently the source of an interrupt is set to 1,

the interrupt pin will be de-asserted. A register pair write is described in Section 7.1 and a

Table 21.

Pull-up/pull-down selection port 0 register (address 48h)

Bit

Symbol

PUD0.7

PUD0.6

PUD0.5

PUD0.4

PUD0.3

PUD0.2

PUD0.1

PUD0.0

Default

Table 22.

Pull-up/pull-down selection port 1 register (address 49h)

Bit

Symbol

PUD1.7

PUD1.6

PUD1.5

PUD1.4

PUD1.3

PUD1.2

PUD1.1

PUD1.0

Default

Table 23.

Interrupt mask port 0 register (address 4Ah) bit description

Bit

Symbol

M0.7

M0.6

M0.5

M0.4

M0.3

M0.2

M0.1

M0.0

Default

Table 24.

Interrupt mask port 1 register (address 4Bh) bit description

Bit

Symbol

M1.7

M1.6

M1.5

M1.4

M1.3

M1.2

M1.1

M1.0

Default

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