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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PCAL9535APW датащи(PDF) 21 Page - NXP Semiconductors |
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PCAL9535APW датащи(HTML) 21 Page - NXP Semiconductors |
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21 / 46 page  PCAL9535A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 28 September 2012 21 of 46 NXP Semiconductors PCAL9535A Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O 8.2 Output drive strength control The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can be configured independently to one of the four possible output current levels. By programming these bits the user is changing the number of transistor pairs or ‘fingers’ that drive the I/O pad. Figure 16 shows a simplified output stage. The behavior of the pad is affected by the Configuration register, the output port data, and the current control register. When the Current Control register bits are programmed to 10b, then only two of the fingers are active, reducing the current drive capability by 50 %. Fig 14. High value resistor in parallel with the LED Fig 15. Device supplied by a lower voltage 002aag164 LED VDD Pn 100 kΩ VDD 002aag165 LED VDD Pn 3.3 V 5 V Fig 16. Simplified output stage VDD P0_0 to P0_7 P1_0 to P1_7 Configuration register 002aah431 DECODER PMOS_EN0 PMOS_EN1 PMOS_EN2 PMOS_EN3 NMOS_EN3 NMOS_EN2 NMOS_EN1 NMOS_EN0 Output port register Current Control register PMOS_EN[3:0] NMOS_EN[3:0] |
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