41594B datasheet(202/372 Pages) MICROCHIP

202 / 372 page

PIC12LF1840T48A

DS41594B-page 202

Preliminary

 2011-2012 Microchip Technology Inc.

24.4.5

PWM STEERING MODE

In Single Output mode, PWM steering allows any of the

PWM pins to be the modulated signal. Additionally, the

same PWM signal can be simultaneously available on

multiple pins.

Once

the

Single

Output

mode

selected

(CCP1M<3:2> = 11 and P1M<1:0> = 00 of the

CCP1CON register), the user firmware can bring out

the same PWM signal to one or two output pins by

setting the appropriate STR1 bits of the PSTR1CON

While the PWM Steering mode is active, the

CCP1M<1:0> bits of the CCP1CON register determine

the polarity of the output pins.

The PWM auto-shutdown operation also applies to

PWM Steering mode as described in Section 24.4.2

“Enhanced PWM Auto-shutdown mode”. An auto-

shutdown event will only affect pins that have PWM

outputs enabled.

FIGURE 24-14:

SIMPLIFIED STEERING

BLOCK DIAGRAM

24.4.5.1

Steering Synchronization

The STR1SYNC bit of the PSTR1CON register gives

the user two selections of when the steering event will

happen. When the STR1SYNC bit is ‘0’, the steering

event will happen at the end of the instruction that

writes to the PSTR1CON register. In this case, the

output signal at the output pins may be an incomplete

PWM waveform. This operation is useful when the user

firmware needs to immediately remove a PWM signal

from the pin.

When the STR1SYNC bit is ‘1’, the effective steering

update will happen at the beginning of the next PWM

period. In this case, steering on/off the PWM output will

always produce a complete PWM waveform.

Figures 24-15 and 24-16 illustrate the timing diagrams

of the PWM steering depending on the STR1SYNC

setting.

24.4.6

START-UP CONSIDERATIONS

When any PWM mode is used, the application

hardware must use the proper external pull-up and/or

pull-down resistors on the PWM output pins.

The CCP1M<1:0> bits of the CCP1CON register allow

the user to choose whether the PWM output signals are

active-high or active-low for each of the PWM output

pins (P1A and P1B). The PWM output polarities must

be selected before the PWM pin output drivers are

enabled. Changing the polarity configuration while the

PWM

output

drivers

are

enable

not

recommended since it may result in damage to the

application circuits.

The P1A and P1B output latches may not be in the

proper states when the PWM module is initialized.

Enabling the PWM pin output drivers at the same time

as the Enhanced PWM modes may cause damage to

the application circuit. The Enhanced PWM modes

must be enabled in the proper Output mode and

complete a full PWM cycle before enabling the PWM

pin output drivers. The completion of a full PWM cycle

is indicated by the TMR2IF bit of the PIR1 register

being set as the second PWM period begins.

Note:

The associated TRIS bits must be set to

output (‘0’) to enable the pin output driver

in order to see the PWM signal on the pin.

TRIS

P1A pin

PORT Data

P1A Signal

STR1A

TRIS

P1B pin

PORT Data

STR1B

Note 1: Port outputs are configured as shown when

the CCP1CON register bits P1M<1:0> = 00

and CCP1M<3:2> = 11.

2: Single PWM output requires setting at least

one of the STR1 bits.

CCP1M1

CCP1M0

Note:

When the microcontroller is released from

Reset, all of the I/O pins are in the high-

impedance state. The external circuits

must keep the power switch devices in the

Off state until the microcontroller drives

the I/O pins with the proper signal levels or

activates the PWM output(s).

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