41594B datasheet(90/372 Pages) MICROCHIP

90 / 372 page

PIC12LF1840T48A

DS41594B-page 90

Preliminary

 2011-2012 Microchip Technology Inc.

9.1.1

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP instruction

- SLEEP instruction will execute as a NOP.

- WDT and WDT prescaler will not be cleared

-TO bit of the STATUS register will not be set

-PD bit of the STATUS register will not be

cleared.

• If the interrupt occurs during or after the execu-

tion of a SLEEP instruction

- SLEEP instruction will be completely exe-

cuted

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

-TO bit of the STATUS register will be set

-PD bit of the STATUS register will be cleared.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

FIGURE 9-1:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

TABLE 9-1:

SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

IOCAF

—

IOCAF5

IOCAF4

IOCAF3

IOCAF2

IOCAF1

IOCAF0

118

IOCAN

—

IOCAN5

IOCAN4

IOCAN3

IOCAN2

IOCAN1

IOCAN0

118

IOCAP

—

IOCAP5

IOCAP4

IOCAP3

IOCAP2

IOCAP1

IOCAP0

118

PIE1

TMR1GIE

ADIE

RCIE

TXIE

SSP1IE

CCP1IE

TMR2IE

TMR1IE

PIE2

OSFIE

—C1IE

EEIE

BCL1IE

—

PIR1

TMR1GIF

ADIF

RCIF

TXIF

SSP1IF

CCP1IF

TMR2IF

TMR1IF

PIR2

OSFIF

—C1IF

EEIF

BCL1IF

—

STATUS

—

—TO

WDTCON

—

WDTPS4

WDTPS3

WDTPS2

WDTPS1

WDTPS0

SWDTEN

Legend:

— = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1(1)

CLKOUT(2)

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

Instruction

Fetched

Instruction

Executed

PC + 1

PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency(4)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy Cycle

PC + 2

0004h

0005h

Dummy Cycle

TOST(3)

PC + 2

Note

XT, HS or LP Oscillator mode assumed.

CLKOUT is not available in XT, HS or LP Oscillator modes, but shown here for timing reference.

TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.

GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

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