41594B datasheet(205/372 Pages) MICROCHIP

205 / 372 page

 2011-2012 Microchip Technology Inc.

Preliminary

DS41594B-page 205

PIC12LF1840T48A

CCP1CON: CCP1 CONTROL REGISTER

R/W-00

R/W-0/0

P1M<1:0>

DC1B<1:0>

CCP1M<3:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Reset

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-6

P1M<1:0>: Enhanced PWM Output Configuration bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

If CCP1M<3:2> = 00, 01, 10:

xx = P1A assigned as Capture/Compare input; P1B assigned as port pins(1)

If CCP1M<3:2> = 11:

00 = Single output; P1A modulated; P1B assigned as port pins

01 = Reserved

10 = Half-Bridge output; P1A, P1B modulated with dead-band control

11 = Reserved

bit 5-4

DC1B<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0

CCP1M<3:0>: ECCP1 Mode Select bits

0000 = Capture/Compare/PWM off (resets ECCP1 module)

0001 = Reserved

0010 = Compare mode: toggle output on match

0011 = Reserved

0100 = Capture mode: every falling edge

0101 = Capture mode: every rising edge

0110 = Capture mode: every 4th rising edge

0111 = Capture mode: every 16th rising edge

1000 = Compare mode: initialize ECCP1 pin low; set output on compare match (set CCP1IF)

1001 = Compare mode: initialize ECCP1 pin high; clear output on compare match (set CCP1IF)

1010 = Compare mode: generate software interrupt only; ECCP1 pin reverts to I/O state

1011 = Compare mode: Special Event Trigger (CCP1 resets Timer, sets CCP1IF bit, and starts A/D conversion

if A/D module is enabled)

PWM mode:

1100 = PWM mode: P1A active-high; P1B active-high

1101 = PWM mode: P1A active-high; P1B active-low

1110 = PWM mode: P1A active-low; P1B active-high

1111 = PWM mode: P1A active-low; P1B active-low

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