41594B datasheet(198/372 Pages) MICROCHIP

198 / 372 page

PIC12LF1840T48A

DS41594B-page 198

Preliminary

 2011-2012 Microchip Technology Inc.

24.4.1

HALF-BRIDGE MODE

In Half-Bridge mode, two pins are used as outputs to

drive push-pull loads. The PWM output signal is output

on the CCP1/P1A pin, while the complementary PWM

output signal is output on the P1B pin (see Figure 24-9).

This mode can be used for half-bridge applications, as

shown in Figure 24-9, or for full-bridge applications,

where four power switches are being modulated with

two PWM signals.

In Half-Bridge mode, the programmable dead-band delay

can be used to prevent shoot-through current in half-

bridge power devices. The value of the P1DC<6:0> bits of

the PWM1CON register sets the number of instruction

cycles before the output is driven active. If the value is

greater than the duty cycle, the corresponding output

remains inactive

during

the

entire

cycle.

See

Section 24.4.4 “Programmable Dead-Band Delay

Mode” for more details of the dead-band delay

operations.

Since the P1A and P1B outputs are multiplexed with

the PORT data latches, the associated TRIS bits must

be cleared to configure P1A and P1B as outputs.

FIGURE 24-8:

EXAMPLE OF HALF-

BRIDGE PWM OUTPUT

FIGURE 24-9:

EXAMPLE OF HALF-BRIDGE APPLICATIONS

Period

Pulse Width

(1)

P1A(2)

P1B(2)

td = Dead-Band Delay

Period

(1)

Note 1: At this time, the TMR2 register is equal to the

PR2 register.

2: Output signals are shown as active-high.

P1A

P1B

FET

Driver

FET

Driver

Load

FET

Driver

FET

Driver

V+

Load

FET

Driver

FET

Driver

P1A

P1B

Standard Half-Bridge Circuit (“Push-Pull”)

Half-Bridge Output Driving a Full-Bridge Circuit

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