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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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41594B датащи(PDF) 195 Page - Microchip Technology |
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41594B датащи(HTML) 195 Page - Microchip Technology |
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195 / 372 page  2011-2012 Microchip Technology Inc. Preliminary DS41594B-page 195 PIC12LF1840T48A 24.3.6 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 24.3.7 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 5.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details. 24.3.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 24.3.9 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a reset, see Section 12.1 “Alternate Pin Function” for more information. TABLE 24-7: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL CCP1SEL 110 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 205 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 83 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 84 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 86 PR2 Timer2 Period Register 173* T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 175 TMR2 Timer2 Module Register 173 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 113 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. |
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