41594B datasheet(196/372 Pages) MICROCHIP

196 / 372 page

PIC12LF1840T48A

DS41594B-page 196

Preliminary

 2011-2012 Microchip Technology Inc.

24.4

PWM (Enhanced Mode)

The enhanced PWM mode generates a Pulse-Width

Modulation (PWM) signal on up to two different output

pins with up to 10 bits of resolution. The period, duty

cycle, and resolution are controlled by the following

registers:

• PR2 registers

• T2CON registers

• CCPR1L registers

• CCP1CON registers

The ECCP modules have the following additional PWM

registers which control Auto-shutdown, Auto-restart,

Dead-band Delay and PWM Steering modes:

• CCP1AS registers

• PSTR1CON registers

• PWM1CON registers

The enhanced PWM module can generate the following

three PWM Output modes:

• Single PWM

• Half-Bridge PWM

• Single PWM with PWM Steering Mode

To select an Enhanced PWM Output mode, the P1M bits

of the CCP1CON register must be configured

appropriately.

The PWM outputs are multiplexed with I/O pins and are

designated P1A and P1B. The polarity of the PWM pins

is configurable and is selected by setting the bits

CCP1M<3:0> in the CCP1CON register appropriately.

Figure 24-5 shows an example of a simplified block

diagram of the Enhanced PWM module.

Table 24-8 shows the pin assignments for various

Enhanced PWM modes.

FIGURE 24-5:

EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE

Note 1: The corresponding TRIS bit must be

cleared to enable the PWM output on the

CCP1 pin.

2: Clearing the CCP1CON register will

relinquish control of the CCP1 pin.

3: Any pin not used in the enhanced PWM

mode is available for alternate pin

functions, if applicable.

4: To

prevent the generation of an

incomplete waveform when the PWM is

first enabled, the ECCP module waits

until the start of a new PWM period

before generating a PWM signal.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(1)

Duty Cycle Registers

DC1B<1:0>

Clear Timer,

toggle PWM pin and

latch duty cycle

Note 1:

The 8-bit timer TMR1 register is concatenated with the 2-bit internal Q clock, or two bits of the prescaler to create the 10-bit time

base.

TRISx

CCP1/P1A

TRISx

P1B

Output

Controller

P1M<1:0>

CCP1M<3:0>

PWM1CON

CCP1/P1A

P1B

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