41594B datasheet(207/372 Pages) MICROCHIP

207 / 372 page

 2011-2012 Microchip Technology Inc.

Preliminary

DS41594B-page 207

PIC12LF1840T48A

PWM1CON: ENHANCED PWM CONTROL REGISTER

R/W-0/0

P1RSEN

P1DC<6:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

P1RSEN: PWM Restart Enable bit

1 = Upon auto-shutdown, the CCP1ASE bit clears automatically once the shutdown event goes

away; the PWM restarts automatically

0 = Upon auto-shutdown, CCP1ASE must be cleared in software to restart the PWM

bit 6-0

P1DC<6:0>: PWM Delay Count bits

P1DC1 = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal

should transition active and the actual time it transitions active

Note 1:

Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe

mode is enabled.

PSTR1CON: PWM STEERING CONTROL REGISTER(1)

U-0

R/W-0/0

R/W-1/1

—

—STR1SYNC

Reserved

STR1B

STR1A

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-5

Unimplemented: Read as ‘0’

bit 4

STR1SYNC: Steering Sync bit

1 = Output steering update occurs on next PWM period

0 = Output steering update occurs at the beginning of the instruction cycle boundary

bit 3-2

Reserved: Read as ‘0’. Maintain these bits clear.

bit 1

STR1B: Steering Enable bit B

1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0>

0 = P1B pin is assigned to port pin

bit 0

STR1A: Steering Enable bit A

1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0>

0 = P1A pin is assigned to port pin

Note 1:

The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> = 11 and

P1M<1:0> = 00.

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