SAM3X datasheet(61/71 Pages) ATMEL

61 / 71 page

11057BS–ATARM–13-Jul-12

SAM3X/A

11057BS–ATARM–13-Jul-12

SAM3X/A

– Each Slot for either a High Speed MultiMediaCard Bus (Up to 30 Cards) or an SD

Memory Card

• Support for Stream, Block and Multi-block Data Read and Write

• Supports Connection to DMA Controller (DMAC)

– Minimizes Processor Intervention for Large Buffer Transfers

• Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental

Access

• Support for CE-ATA Completion Signal Disable Command

• Protection Against Unexpected Modification On-the-Fly of the Configuration Registers

12.9

USB On-The-Go High Speed Port (UOTGHS)

• USB2.0 Compliant, Low/Full/High-Speed (LS/FS/HS) and On-The-Go, 1.5Mb/s, 12Mb/s,

480Mb/s

• 10 Pipes/Endpoints

• 4K bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints

• Up to 2 Memory Banks per Pipe/Endpoint (Not for Control Pipe/Endpoint)

• Flexible Pipe/Endpoint Configuration and Management with 6 Dedicated DMA Channels

• On-Chip UTMI transceiver including Pull-ups/Pull-downs

• On-Chip OTG pad including VBUS analog comparator

12.10 Analog-to-Digital Converter (ADC)

• 12-bit Resolution

• 1 MHz Conversion Rate

• 2.4 V to 3.6 V Wide Range Power Supply Operation

• Selectable Single Ended or Differential Input Voltage

• Programmable Gain and Offset per channel For Maximum Full Scale Input Range 0 - VDD

• Integrated Multiplexer Offering Up to 16 Independent Analog Inputs

• Individual Enable and Disable of Each Channel

• Hardware or Software Trigger

– External Trigger Pin

– Timer Counter Outputs (Corresponding TIOA Trigger)

– Internal Trigger Counter

– PWM Event Line

• Drive of PWM Fault Input

• PDC Support

• Possibility of ADC Timings Configuration

• Two Sleep Modes and Conversion Sequencer

– Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all

Enabled Channels

– Possibility of Customized Channel Sequence

• Standby Mode for Fast Wakeup Time Response

– Power Down Capability

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