SAM3X datasheet(28/71 Pages) ATMEL

28 / 71 page

11057BS–ATARM–13-Jul-12

SAM3X/A

11057BS–ATARM–13-Jul-12

SAM3X/A

Note:

1. If PC0 is used as PIO input in user applications, a low level must be ensured at startup to pre-

vent Flash erase before the user application sets PC0 into PIO mode.

6.2.1

Serial Wire JTAG Debug Port (SWJ-DP) Pins

The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on

a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference

and reset state, refer to Table 3-1.

At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging

probe. Please refer to the “Debug and Test” section of the product datasheet.

SWJ-DP pins can be used as standard I/Os to provide users with more general input/output pins

when the debug port is not needed in the end application. Mode selection between SWJ-DP

mode (System IO mode) and general IO mode is performed through the AHB Matrix Special

Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing

and glitch filters is possible regardless of the mode.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It

integrates a permanent pull-down resistor of about 15 k

Ω to GND, so that it can be left uncon-

nected for normal operations.

By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial

Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and

TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire

Debug Port is active, TDO/TRACESWO can be used for trace.

The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous

trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and

JTAG-DP switching, please refer to the “Debug and Test” section of the product datasheet.

All JTAG signals are supplied with VDDIO except JTAGSEL, supplied by VDDBU.

6.3

Test Pin

The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming

mode of the SAM3X/A series. The TST pin integrates a permanent pull-down resistor of about

15 k

Ω to GND, so that it can be left unconnected for normal operations. To enter fast program-

ming mode, see the “Fast Flash Programming Interface” section. For more information on the

manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet.

Table 6-1.

System I/O Configuration Pin List

SYSTEM_IO

Bit Number

Peripheral

Default Function

After Reset

Other Function

Constraints for

Normal Start

Configuration

ERASE

PC0

Low Level at

startup

()

In Matrix User Interface Registers

(Refer to “System IO Configuration

of the product datasheet.)

TCK/SWCLK

PB28

In PIO Controller

TDI

PB29

TDO/TRACESWO

PB30

TMS/SWDIO

PB31

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