SAM3X datasheet(32/71 Pages) ATMEL

32 / 71 page

11057BS–ATARM–13-Jul-12

SAM3X/A

11057BS–ATARM–13-Jul-12

SAM3X/A

7.6

DMA Controller

• Acting as one Matrix Master

• Embeds 4 (SAM3A and 100-pin SAM3X) or 6 (144-pin SAM3X) channels

• Linked List support with Status Write Back operation at End of Transfer

• Word, HalfWord, Byte transfer support.

• Handles high speed transfer of SPI0-1, USART0-1, SSC and HSMCI (peripheral to memory,

memory to peripheral)

• Memory to memory transfer

• Can be triggered by PWM and T/C which enables to generates waveform though the

External Bus Interface

The DMA controller can handle the transfer between peripherals and memory and so receives

the triggers from the peripherals below. The hardware interface numbers are also given in Table

7-5.

Table 7-4.

DMA Channels

DMA Channel Size

SAM3A

100-pin SAM3X

144-pin SAM3X

8 bytes FIFO for Channel Buffering

(Channels 0, 1 and 2)

(Channels 0, 1, 2 and 4)

32 bytes FIFO for Channel Buffering

(Channel 3)

(Channels 3 and 5)

Table 7-5.

DMA Controller

Instance Name

Channel T/R

DMA Channel HW

Interface Number

HSMCI

Transmit/Receive

SPI0

Transmit

SPI0

Receive

SSC

Transmit

SSC

Receive

SPI1

Transmit

SPI1

Receive

TWI0

Transmit

TWI0

Receive

USART0

Transmit

USART0

Receive

USART1

Transmit

USART1

Receive

PWM

Transmit

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