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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM9712CLGEFL/V датащи(PDF) 67 Page - Wolfson Microelectronics plc |
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WM9712CLGEFL/V датащи(HTML) 67 Page - Wolfson Microelectronics plc |
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67 / 78 page  Production Data WM9712L w PD, Rev 4.6, November 2011 67 Register 26h is for power management according to the AC’97 specification. Note that the actual state of many circuit blocks depends on both register 24h AND register 26h. REG ADDR BIT LABEL DEFAULT DESCRIPTION REFER TO 14 PR6 see note Disables HPOUTL, HPOUTR and OUT3 Buffer Power Management 13 PR5 Disables Internal Clock 12 PR4 Disables AC-link interface (external clock off) 11 PR3 Disables VREF, analogue mixers and outputs 10 PR2 Disables analogue mixers, LOUT2, ROUT2 (but not VREF) 9 PR1 Disables Stereo DAC and AUXDAC 8 PR0 Disables audio ADCs and input Mux 3 REF inverse of PR2 Read-only bit, Indicates VREF is ready 2 ANL inverse of PR3 Read-only bit, indicates analogue mixers are ready 1 DAC inverse of PR1 Read-only bit, indicates audio DACs are ready 0 ADC inverse of PR0 Read-only bit, indicates audio ADCs are ready Note: PR6 to PR0 default to 1 if pin 47 is held high during reset, otherwise they default to 0. Register 28h is a read-only register that indicates to the driver which advanced AC’97 features the WM9712L supports. REG ADDR BIT LABEL DEFAULT DESCRIPTION REFER TO 28h 15:14 ID 00 Indicates that the WM9712L is configured as the primary CODEC in the system. Intel’s AC’97 Component Specification, Revision 2.2, page 59 11:10 REV 01 Indicates that the WM9712L conforms to AC’97 Rev2.2 9 AMAP 0 Indicates that the WM9712L does not support slot mapping 8 LDAC 0 Indicates that the WM9712L does not have an LFE DAC 7 SDAC 0 Indicates that the WM9712L does not have Surround DACs 6 CDAC 0 Indicates that the WM9712L does not have a Centre DAC 3 VRM 0 Indicates that the WM9712L does not have a dedicated, variable rate microphone ADC 2 SPDIF 1 Indicates that the WM9712L supports SPDIF output 1 DRA 0 Indicates that the WM9712L does not support double rate audio 0 VRA 1 Indicates that the WM9712L supports variable rate audio Register 2Ah controls the SPDIF output and variable rate audio. REG ADDR BIT LABEL DEFAULT DESCRIPTION REFER TO 2Ah 10 SPCV 1 (valid) SPDIF validity bit (read-only) Digital Audio (SPDIF) Output 5:4 SPSA 01 (slots 6, 9) Controls SPDIF slot assignment. 00=slots 3 and 4, 01=6/9, 10=7/8, 11=10/11 2 SEN 0 (OFF) Enables SPDIF output enable 0 VRA 0 (OFF) Enables variable rate audio Registers 2Ch, 2Eh 32h and control the sample rates for the stereo DAC, auxiliary DAC and audio ADC, respectively. REG ADDR BIT LABEL DEFAULT DESCRIPTION REFER TO 2Ch all DACSR BB80h Controls stereo DAC sample rate Variable Rate Audio / Sample Rate Conversion 2Eh all AUXDACSR BB80h Controls auxiliary DAC sample rate 32h all ADCSR BB80h Controls audio ADC sample rate Note: The VRA bit in register 2Ah must be set first to obtain sample rates other than 48kHz |
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