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WM9712CLGEFL/V датащи(PDF) 59 Page - Wolfson Microelectronics plc

номер детали WM9712CLGEFL/V
подробное описание детали  AC??7 Audio and Touchpanel CODEC
PDF  78 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM9712CLGEFL/V датащи(HTML) 59 Page - Wolfson Microelectronics plc

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Production Data
WM9712L
w
PD, Rev 4.6, November 2011
59
INTERFACE TIMING
Test Characteristics:
DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, TA = -25C to +85C, unless otherwise stated.
CLOCK SPECIFICATIONS
BITCLK
SYNC
t
CLK_HIGH
t
CLK_LOW
t
CLK_PERIOD
t
SYNC_HIGH
t
SYNC_LOW
t
SYNC_PERIOD
Figure 17 Clock Specifications (50pF External Load)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
BITCLK frequency
12.288
MHz
BITCLK period
tCLK_PERIOD
81.4
ns
BITCLK output jitter
750
ps
BITCLK high pulse width (Note 1)
tCLK_HIGH
36
40.7
45
ns
BITCLK low pulse width (Note 1)
tCLK_LOW
36
40.7
45
ns
SYNC frequency
48
kHz
SYNC period
tSYNC_PERIOD
20.8
s
SYNC high pulse width
tSYNC_HIGH
1.3
s
SYNC low pulse width
tSYNC_LOW
19.5
s
Note:
1. Worst case duty cycle restricted to 45/55
DATA SETUP AND HOLD
Figure 18 Data Setup and Hold (50pF External Load)
Note:
Setup and hold times for SDATAIN are with respect to the AC’97 controller, not the WM9712L.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Setup to falling edge of BITCLK
tSETUP
10
ns
Hold from falling edge of BITCLK
tHOLD
10
ns
Output valid delay from rising edge of
BITCLK
tCO
15
ns



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