WM9712CLGEFLSLASHV datasheet(56/78 Pages) WOLFSON

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WM9712L

Production Data

PD, Rev 4.6, November 2011

Table 42 Extended Power Down Register (Additional to AC’97 Rev 2.2)

Note:

*When disabling a PGA, always ensure that it is muted first.

ADDITIONAL POWER MANAGEMENT:



AUXDAC: see “Auxiliary DAC” section. AUXDAC is OFF by default.



Touchpanel Interface: see “Controlling the Touchpanel Digitiser / Power Management”.

The touchpanel digitiser is OFF by default.

SLEEP MODE

Whenever the PR4 bit (reg. 26h) is set, the AC-Link interface is disabled, and the WM9712L is in

sleep mode. There is in fact a very large number of different sleep modes, depending on the other

control bits. For example, the low-power standby mode described below is a sleep mode. It is

desirable to use sleep modes whenever possible, as this will save power. The following functions do

not require a clock and can therefore operate in sleep mode:



Analogue-to-analogue audio (DACs and ADCs unused), e.g. phone call mode



Pen-down detection



GPIO and interrupts



Battery alarm / analogue comparators (but not battery measurement)

The WM9712L can awake from sleep mode as a result of



A warm reset on the AC-Link (according to the AC’97 specification)



A signal on a GPIO pin (if the pin is configured as an input, with wake-up enabled – see

“GPIO and Interrupt Control” section)



A virtual GPIO event such as pen-down, battery alarm, etc. (see “GPIO and Interrupt

Control” section)

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

24h

Additional

power down

control

PD15

0 (ON)

Disables Crystal Oscillator

PD14

0 (ON)

Disables left audio DAC

PD13

0 (ON)

Disables right audio DAC

PD12

0 (ON)

Disables left audio ADC

PD11

0 (ON)

Disables right audio ADC

PD10

0 (ON)

Disables MICBIAS

PD9

0 (ON)

Disables left headphone mixer

PD8

0 (ON)

Disables right headphone mixer

PD7

0 (ON)

Disables speaker mixer

PD6

0 (ON)

Disables MONO_OUT buffer (pin 33) and phone

mixer

PD5

0 (ON)

Disables OUT3 buffer (pin 37)

PD4

0 (ON)

Disables headphone buffers (HPOUTL/R)

PD3

0 (ON)

Disables speaker outputs (LOUT2, ROUT2)

PD2

0 (ON)

Disables Line Input PGA (left and right) *

PD1

0 (ON)

Disables Phone Input PGA *

PD0

0 (ON)

Disables Mic Input PGA (left and right) *

Note: When analogue inputs or outputs are disabled, they are internally connected to VREF

through a large resistor (VREF=AVDD/2 except in OFF mode, when VREF itself is disabled). This

maintains the potential at that node and helps to eliminate pops when the pins are re-enabled.

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