HT45F12 datasheet(43/104 Pages) HOLTEK

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HT45F12

8-Bit Flash MCU with Op Amps & Comparators

HT45F12

8-Bit Flash MCU with Op Amps & Comparators

SLOW Mode to NORMAL Mode Switching

InSLOWModethesystemusestheLIRClowspeedsystemoscillator.Toswitchbacktothe

NORMALMode,wherethehighspeedsystemoscillatorisused,theHLCLKbitshouldbesetto

“1”orHLCLKbitis“0”,butLCKS2~LCKS0issetto“010”,“011”,“100”,“101”,“110”or“111”.

Asacertainamountoftimewillberequiredforthehighfrequencyclocktostabilise,thestatusof

theHTObitischecked.Theamountoftimerequiredforhighspeedsystemoscillatorstabilization

dependsuponwhichhighspeedsystemoscillatortypeisused.

Entering the SLEEP0 Mode

ThereisonlyonewayforthedevicetoentertheSLEEP0Modeandthatistoexecutethe“HALT”

instructionintheapplicationprogramwiththeIDLENbitinSYSMODregisterequalto“0”andthe

WDTisoff.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowing

willoccur:

Thesystemclock,WDTclockandTimeBaseclockwillbestoppedandtheapplicationprogram

willstopatthe“HALT”instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandstopped

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,

willbecleared.

Entering the SLEEP1 Mode

ThereisonlyonewayforthedevicetoentertheSLEEP1Modeandthatistoexecutethe“HALT”

instructionintheapplicationprogramwiththeIDLENbitinSYSMODregisterequalto“0”andtheWDT

ison.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe

“HALT”instruction,buttheWDTwillremainwiththeclocksourcecomingfromthefLclock.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandresumecountingastheWDTisenabled.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,

willbecleared.

Entering the IDLE0 Mode

ThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”

instructionintheapplicationprogramwiththeIDLENbitinSYSMODregisterequalto“1”andthe

FSYSONbitinCTRLregisterequalto“0”.Whenthisinstructionisexecutedundertheconditions

describedabove,thefollowingwilloccur:

• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction,

buttheTimeBaseclockandfSUBclockwillbeon.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandresumecountingiftheWDTisenabled.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,

willbecleared.

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