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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HT45F12 датащи(PDF) 39 Page - Holtek Semiconductor Inc |
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HT45F12 датащи(HTML) 39 Page - Holtek Semiconductor Inc |
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39 / 104 page  Rev. 0.00 38 �e�te��e� ��� �01� Rev. 0.00 39 �e�te��e� ��� �01� HT45F12 8-Bit Flash MCU with Op Amps & Comparators HT45F12 8-Bit Flash MCU with Op Amps & Comparators Control Register Asingleregister,SYSMOD,isusedforoverallcontroloftheinternalclockswithinthedevice. SYSMOD Register Bit 7 6 5 4 3 2 1 0 Na�e LCK�� LCK�1 LCK�0 F�TEN LTO HTO IDLEN HLCLK R/W R/W R/W R/W R/W R R R/W R/W POR 0 0 0 0 0 0 1 1 bit7~5 LCKS2 ~ LCKS0:ThesystemclockselectionwhenHLCLKis“0” 000:fL(fLIRC) 001:fL(fLIRC) 010:fH/64 011:fH/32 100:fH/16 101:fH/8 110:fH/4 111:fH/2 Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.In additiontothesystemclocksource,whichcanbeLIRC,adividedversionofthehigh speedsystemoscillatorcanalsobechosenasthesystemclocksource. Bit4 FSTEN:FastWake-upControl(onlyforHXT) 0:Disable 1:Enable ThisistheFastWake-upControlbitwhichdeterminesifthefSUBclocksourceis initiallyusedafterthedevicewakesup.Whenthebitishigh,thefSUBclocksourcecan beusedasatemporarysystemclocktoprovideafasterwakeuptimeasthefSUBclock isavailable. bit3 LTO:LIRCSystemOSCSSTreadyflag 0:Notready 1:Ready ThisisthelowspeedsystemoscillatorSSTreadyflagwhichindicateswhenthelow speedsystemoscillatorisstableafterpoweronresetorawake-uphasoccurred.The flagwillbelowwhenintheSLEEP0Modebutafterawake-uphasoccurred,theflag willchangetoahighlevelafter1~2clockcyclesiftheLIRCoscillatorisused. bit2 HTO:HIRCSystemOSCSSTreadyflag 0:Notready 1:Ready ThisisthehighspeedsystemoscillatorSSTreadyflagwhichindicateswhenthe highspeedsystemoscillatorisstableafterawake-uphasoccurred.Theflagwill belowwhenintheSLEEPorIDLE0Modebutafterpoweronresetorawake-up hasoccurred,theflagwillchangetoahighlevelafter1024clockcyclesiftheHXT oscillatorisusedandafter15~16clockcyclesiftheERCorHIRCoscillatorisused. bit1 IDLEN:IDLEModeControl 0:Disable 1:Enable ThisistheIDLEModeControlbitanddetermineswhathappenswhentheHALT instructionisexecuted.Ifthisbitishigh,whenaHALTinstructionisexecutedthe devicewillentertheIDLEMode.IntheIDLE1ModetheCPUwillstoprunning butthesystemclockwillcontinuetokeeptheperipheralfunctionsoperational,if FSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstop inIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALT instructionisexecuted. |
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