CXD3003 datasheet(122/137 Pages) SONY

122 / 137 page

– 122 –

CXD3003R

$3E (preset: $3E 00 00)

F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage

On when set to 1; default = 0.

F1NM: Gain normal

F1DM: Gain down

T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage

On when set to 1; default = 0.

T1NM: Gain normal

T1UM: Gain up

F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage

On when set to 1; default = 0.

Generally, the advance amount of the phase becomes large by partially setting the FCS servo

third-stage filter which is used as the phase compensation filter to double accuracy.

F3NM: Gain normal

F3DM: Gain down

T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage

On when set to 1; default = 0.

Generally, the advance amount of the phase becomes large by partially setting the TRK servo

third-stage filter which is used as the phase compensation filter to double accuracy.

T3NM: Gain normal

T3UM: Gain up

Note) Filter first- and third-stage quasi double accuracy settings can be set individually.

See "FILTER Composition" at the end of this specification concerning quasi double accuracy.

DFIS:

FCS hold filter input extraction node selection

0: M05 (Data RAM address 05); default

1: M04 (Data RAM address 04)

TLCD:

This command masks the TLC2 command set by D2 of $38 only when FOK is low.

On when set to 1; default = 0

LKIN:

When 0, the internally generated LOCK signal is output to the LOCK pin. (default)

When 1, the LOCK signal can be input from an external source to the LOCK pin.

COIN:

When 0, the internally generated COUT signal is output to the COUT pin. (default)

When 1, the COUT signal can be input from an external source to the COUT pin.

The MIRR, DFCT and FOK signals can also be input from an external source.

MDFI:

When 0, the MIRR, DFCT and FOK signals are generated internally. (default)

When 1, the MIRR, DFCT and FOK signals can be input from an external source through the

MIRR, DFCT and FOK pins.

MIRI:

When 0, the MIRR signal is generated internally. (default)

When 1, the MIRR signal can be input from an external source through the MIRR pin.

D15

D14

D13

D12

D11

D10

F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD

LKIN COIN MDFI MIRI XT1D

XT1D:

The clock input from FSTI can be used without being frequency-divided as the master clock for

the servo block by setting D0 to 1. This command takes precedence over the XTSL pin, XT2D

and XT4D. See the description of $3F for XT2D and XT4D.

MDFI

—

MIRR, DFCT and FOK are all generated internally.

MIRR only is input from an external source.

MIRR, DFCT and FOK are all input from an external source.

MIRI

∗

∗: preset, —: don't care

CXD3003 датащи(PDF) 122 Page - Sony Corporation

CXD3003 датащи(HTML) 122 Page - Sony Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL