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CXD3003 датащи(PDF) 37 Page - Sony Corporation

номер детали CXD3003
подробное описание детали  CD Digital Signal Processor with Built-in Digital Servo and DAC
PDF  137 Pages
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производитель  SONY [Sony Corporation]
домашняя страница  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXD3003 датащи(HTML) 37 Page - Sony Corporation

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CXD3003R
Command bit
Processing
VCOSEL1 = 0
VCOSEL1 = 1
Multiplier PLL VCO1 is set to normal speed.
Multiplier PLL VCO1 is set to approximately twice the normal speed.
Command bit
KSL3
KSL2
Processing
Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/1 frequency-divided.
Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/2 frequency-divided.
Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/4 frequency-divided.
Output of multiplier PLL VCO1 selected by VCO1 CS1 and CS0 is 1/8 frequency-divided.
0
0
1
1
0
1
0
1
∗ This setting is valid only when the low-speed VCO is selected by VCO1 CS1 and CS0.
See the previous page.
Command
Data 2
MODE
specification
VCO
SEL1
ASHS SOCT
VCO
SEL2
D19
D18
D17
D16
Data 3
KSL3
KSL2
KSL1
KSL0
D15
D14
D13
D12
Command bit
Processing
VCOSEL2 = 0
VCOSEL2 = 1
Wide-band PLL VCO2 is set to normal speed.
Wide-band PLL VCO2 is set to approximately twice the normal speed.
Command bit
KSL1
KSL0
Processing
Output of wide-band PLL VCO2 selected by VCO2 CS is 1/1 frequency-divided.
Output of wide-band PLL VCO2 selected by VCO2 CS is 1/2 frequency-divided.
Output of wide-band PLL VCO2 selected by VCO2 CS is 1/4 frequency-divided.
Output of wide-band PLL VCO2 selected by VCO2 CS is 1/8 frequency-divided.
0
0
1
1
0
1
0
1
∗ This setting is valid only when the low-speed VCO is selected by VCO2 CS.



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