CXD3003 datasheet(15/137 Pages) SONY

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CXD3003R

Contents

[1] CPU Interface

§1-1.

CPU Interface Timing ........................................................................................................................ 16

§1-2.

CPU Interface Command Table ........................................................................................................ 16

§1-3.

CPU Command Presets .................................................................................................................... 26

§1-4.

Description of SENS Signals ............................................................................................................. 31

[2] Subcode Interface

§2-1.

P to W Subcode Readout .................................................................................................................. 65

§2-2.

80-bit Sub Q Readout ........................................................................................................................ 65

[3] Description of Modes

§3-1.

CLV-N Mode ...................................................................................................................................... 71

§3-2.

CLV-W Mode ..................................................................................................................................... 71

§3-3.

CAV-W Mode ..................................................................................................................................... 71

§3-4.

VCO-C Mode ..................................................................................................................................... 72

[4] Description of Other Functions

§4-1.

Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 74

§4-2.

Frame Sync Protection ...................................................................................................................... 76

§4-3.

Error Correction ................................................................................................................................. 76

§4-4.

DA Interface ....................................................................................................................................... 77

§4-5.

Digital Out .......................................................................................................................................... 80

§4-6.

Servo Auto Sequence ....................................................................................................................... 81

§4-7.

Digital CLV ......................................................................................................................................... 89

§4-8.

Playback Speed ................................................................................................................................ 90

§4-9.

DAC Block Playback Speed .............................................................................................................. 91

§4-10. DAC Block Input Timing .................................................................................................................... 91

§4-11. Asymmetry Compensation ................................................................................................................ 92

§4-12. CXD3003 Clock System .................................................................................................................... 93

[5] Description of Servo Signal Processing System Functions and Commands

§5-1.

General Description of the Servo Signal Processing System ............................................................ 94

§5-2.

Digital Servo Block Master Clock (MCK) ........................................................................................... 95

§5-3.

AVRG Measurement and Compensation .......................................................................................... 95

§5-4.

E:F Balance Adjustment Function ..................................................................................................... 97

§5-5.

FCS Bias Adjustment Function .......................................................................................................... 97

§5-6.

AGCNTL Function ............................................................................................................................. 99

§5-7.

FCS Servo and FCS Search ........................................................................................................... 101

§5-8.

TRK and SLD Servo Control ........................................................................................................... 102

§5-9.

MIRR and DFCT Signal Generation ................................................................................................ 103

§5-10. DFCT Countermeasure Circuit ........................................................................................................ 104

§5-11. Anti-Shock Circuit ............................................................................................................................ 104

§5-12. Brake Circuit .................................................................................................................................... 105

§5-13. COUT Signal ................................................................................................................................... 106

§5-14. Serial Readout Circuit ...................................................................................................................... 106

§5-15. Writing to the Coefficient RAM ........................................................................................................ 107

§5-16. PWM Output .................................................................................................................................... 107

§5-17. DIRC Input Pin ................................................................................................................................. 109

§5-18. Servo Status Changes Produced by the LOCK Signal ................................................................... 110

§5-19. Description of Commands and Data Sets ....................................................................................... 110

§5-20. List of Servo Filter Coefficients ........................................................................................................ 125

§5-21. Filter Composition ............................................................................................................................ 127

§5-22. TRACKING and FOCUS Frequency Response .............................................................................. 134

[6] Application Circuit .................................................................................................................................. 135

Explanation of abbreviations

AVRG:

Average

AGCNTL: Auto gain control

FCS:

Focus

TRK:

Tracking

SLD:

Sled

DFCT:

Defect

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