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TNETX3100PGC датащи(PDF) 72 Page - Texas Instruments

номер детали TNETX3100PGC
подробное описание детали  ThunderSWITCHE 10-PORT 10-/100-MBIT/S ETHERNETE SWITCH
PDF  80 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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TNETX3100PGC датащи(HTML) 72 Page - Texas Instruments

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TNETX3100
ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH
SPWS031D – JUNE 1997 – REVISED OCTOBER 1997
72
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
operating characteristics over recommended operating conditions (see Figure 23)
EEPROM interface
NO.
PARAMETER
MIN
MAX
UNIT
fclock (ECLK)
Clock frequency, ECLK
98
kHz
1
td (ECLKH–EDIOL)
Delay time, from ECLK
↑ to EDIO↓ (see Note 14)
5
µs
2
td (EDIOL–ECLKL)
Delay time, from EDIO
↓ to ECLK↓ (see Note 14)
5
µs
3
td (ECLKL–EDIOX)
Delay time, from ECLK
↓ to EDIO changing (see Note 15)
0
µs
4
td (EDIOV–ECLKH)
Delay time, from EDIO valid output to ECLK
↑
0
µs
5
td (ECLKL–EDIOV)
Delay time, from ECLK
↓ to EDIO valid
0
µs
6
td (ECLKL–EDIOX)
Delay time, from ECLK
↓ to EDIO changing (see Note 16)
0
µs
7
td (ECLKH–EDIOX)
Delay time, from ECLK
↑ to EDIO invalid
5
µs
8
td (EDIOV–ECLKH)
Delay time, from EDIO valid input to ECLK
↑
10
µs
NOTES: 14. This is a start-condition delay time during ECLK high.
15. This is a changing-data condition delay time for output EDIO.
16. This is a changing-data condition delay time for input EDIO.
7
ECLK
(output)
EDIO
(output)
EDIO
(input)
1
2
5
6
3
4
8
VALID
VALID
VALID
VALID
Figure 23. EEPROM Interface Timing



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