TNETX3100PGC datasheet(36/80 Pages) TI1

36 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

system control register at 0x00D3

BIT

RESET

LOAD

START

CLRSTS

STMAP

SECDIS

LONG

IOBMOD

Initial Values After Reset

BIT

NAME

FUNCTION

RESET

RESET = 1 places the TNETX3100 in a software reset state. Writing a 0 clears the reset state and allows for internal

testing while keeping the ports disabled. RESET clears the port control register but does not affect any other

configuration register. Configuration registers are cleared by a hardware reset (write to DIO address 4000–7FFF).

LOAD

Load system. Writing LOAD = 1 causes the TNETX3100 DIO registers to auto-load from an external EEPROM (if

present). All registers in the DIO address range 0x00–0xC3 are loaded from the corresponding EEPROM locations.

Writing LOAD = 0 has no effect. LOAD is read as a 1 until the auto-load is complete.

LOAD is not auto-loaded. LOAD is always set to 0 by auto-load.

START

Start system. Writing START = 1 causes the TNETX3100 to begin operation. START is read as a 1 until buffer

memory initialization is complete. While buffers are being initialized, all ports are disabled. Writing START = 0 has

no effect.

CLRSTS

Clear statistics. Writing CLRSTS = 1 causes the TNETX3100 to clear all its statistics counters. The TNETX3100

repeats clearing the statistics counters until CLRSTS is cleared.

STMAP

Statistic mapping. STMAP selects which statistic is recorded in multiple-function statistic counters. When

STMAP = 1, the number of TX frames discarded on TX, due to lack of resources, is recorded. If STMAP = 0, the

number of data errors at TX is recorded.

SECDIS

Disable ports on security violations. When SECDIS = 1, address security violations cause a port to be disabled.

When SECDIS = 0, address security violations cause a port to be suspended. Suspended ports are reenabled

when the offending condition is removed. Disabled ports are only reenabled by management (by setting port

ENABLE bit).

LONG

Long-frame handling. When LONG = 1, the RX and TX frame 1024–1518 bucket counter is redefined to become

RX and TX frames 1024–1531. When LONG = 0, the RX and TX frame 1024–1518 bucket counter is operating

normally. Frames 1536 bytes or larger are truncated.

IOBMOD

In-order broadcast mode. Always read as IOBMOD = 1; this is a read-only bit.

DRAM data register at 0x00D4–0x00D7

BIT

DRAMDATA

BIT

NAME

FUNCTION

31–0

DRAMDATA

DRAM data. DRAMDATA holds a 32-bit data value that maps to the forward-pointer field of a DRAM buffer

when accessed in DRAM test-access mode.

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