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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TNETX3100PGC датащи(PDF) 40 Page - Texas Instruments |
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TNETX3100PGC датащи(HTML) 40 Page - Texas Instruments |
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40 / 80 page  TNETX3100 ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH SPWS031D – JUNE 1997 – REVISED OCTOBER 1997 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACTST register at 0x00DE BIT 7 6 5 4 3 2 1 0 FLAG100 FLAG10 Reserved INITPACE Initial Values After Reset — — X 1 1 1 1 1 BIT NAME FUNCTION 7 FLAG100 Pacing flag comparison for all 100-Mbit/s. FLAG100 is the OR of all the 100-Mbit/s port compare signals resulting from the comparison between the pacing register and the initial pace value. When FLAG100 = 1, an error has occurred if all ports are involved in pacing and have experienced similar traffic. When an error is detected, no information is given as to which port signal is in error. When FLAG100 = 0, the TNETX3100 is functioning normally. 6 FLAG10 Pacing flag comparison for all 10-Mbit/s ports. Flag10 is the OR of all the 10-Mbits ports. 5 Reserved Reserved 4–0 INITPACE Pacing register initial value. At reset, bits 4–0 are inverted and loaded into the pacing register (the default value for the register is 00000 and the default loaded value after reset is 11111). Following reset, bits 4–0 are used to compare the contents of the pacing register. The result of the comparison is returned and ORed to form bits 6 and 7 in the PACTST register. address registers at 0x08*A + 0x0100 through 0x08*A + 0x0107 (A = address register in hex, legal values are 1–15) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 (MSB) BIT 2 BIT 1 BIT 0 (LSB) DIO ADDRESS Reserved Reserved Reserved Reserved Reserved Reserved Reserved LOCK† 0x08(A–16) Reserved Reserved Reserved Reserved Port number Port number Port number Port number 0x08(A–16)+0x01 Address Bit 47 Address Bit 46 Address Bit 45 Address Bit 44 Address Bit 43 Address Bit 42 Address Bit 41 Address Bit 40 0x08(A–16)+0x02 Address Bit 39 Address Bit 38 Address Bit 37 Address Bit 36 Address Bit 35 Address Bit 34 Address Bit 33 Address Bit 32 0x08(A–16)+0x03 Address Bit 31 Address Bit 30 Address Bit 29 Address Bit 28 Address Bit 27 Address Bit 26 Address Bit 25 Address Bit 24 0x08(A–16)+0x04 Address Bit 23 Address Bit 22 Address Bit 21 Address Bit 20 Address Bit 19 Address Bit 18 Address Bit 17 Address Bit 16 0x08(A–16)+0x05 Address Bit 15 Address Bit 14 Address Bit 13 Address Bit 12 Address Bit 11 Address Bit 10 Address Bit 9 Address Bit 8 0x08(A–16)+0x06 Address Bit 7 Address Bit 6 Address Bit 5 Address Bit 4 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 0x08(A–16)+0x07 † LOCK is present for network address register 16; for all other network address registers (17–31), LOCK is reserved. address register description The 16 network registers shown in the following tables are combined with the other 16 registers (address 0000 through 007F) for a total of 32 network address registers; they form a 32-deep push-down stack, and this stack holds the last 32 source addresses. |
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