CLK

t

CLK

t

CPWH

t

CPWL

DAC1282

SBAS490

– DECEMBER 2011

www.ti.com

CLOCK INPUT (CLK)

The CLK pin is the master clock input to the DAC1282, nominally 4.096 MHz. As with any high-performance data

converter, a high-quality clock source is essential. A crystal oscillator or low-jitter PLL clock source is

recommended. Make sure to avoid ringing on the input by keeping the trace short and source-terminating

(typically 50

Ω). See the CLK specifications shown in Figure 38 and Table 9.

Figure 38. CLK Timing Requirements

Table 9. Requirements for Figure 38

SYMBOL

DESCRIPTION

MIN

MAX

UNIT

CLK period

235

1000

ns

CLK pulse width high or low

95

900

ns

SWITCH CONTROL/EXTERNAL DIGITAL INPUT (SW/TD)

SW/TD is a multi-function digital input pin. The SW/TD function depends on the mode of operation.

SW Function

In sine, dc, and pulse mode, SW/TD controls the output switch. When SW/TD is low, all switches are forced

open, overriding the switch register setting (SW[2:0]). When SW/TD is high, the switch is transparent to the value

of register setting. In power-down mode, the switch is forced open.

TD Function

In digital input mode, SW/TD is the signal input used to drive the DAC. The data input are modulated by

ones-density and are clocked in by the master clock (CLK). When the ones-density is 75% (that is, on average,

three out of four bits are '1'), the differential output voltage is at the positive maximum value. When the

ones-density is 25% (that is, on average, three out of four bits are '0'), the differential output voltage is at the

negative maximum value. When the ones-density is 50% (on average, an equal number of '0's and '1's), the

differential output is zero.

SW/TD is sampled by the DAC1282 at the rate of CLK/16. Therefore, the sampling can have

±8 CLK periods of

uncertainty. SYNC can be used to eliminate the uncertainty by synchronizing the phase of SW/TD to the desired

CLK cycle. Synchronizing the digital input results in a consistent phase of the output signal; see the SYNC

section.

The output range is set by the analog gain bits, GAIN[2:0]; see Table 3. Equation 3 describes the DAC output

versus the bitstream input ones-density. Make sure to avoid ringing on the input by keeping the trace short. In

some cases, source-terminating resistors may be necessary (20

Ω to 50 Ω).

22

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