UCD3138 datasheet(43/68 Pages) TI1

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A ON SELECT

A OFF SELECT

B ON SELECT

B OFF SELECT

EGEN A

EGEN B

EDGE GEN

PWM A

PWM B

B SELECT

A SELECT

INTRAMUX

A/B/C (N)

A/B/C (N+1)

C (N+2)

C (N+3)

A(N)

B(N)

A(N+1)

B(N+1)

UCD3138

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SLUSAP2 A – MARCH 2012 – REVISED MARCH 2012

4.13 DPWMC, Edge Generation, IntraMux

The UCD31xx has hardware for generating complex waveforms beyond the simple DPWMA and DPWMB

waveforms already discussed – DPWMC, the Edge Generation Module, and the IntraMux.

DPWMC is a signal inside the DPWM logic. It goes high at the Blanking A begin time, and low at the

Blanking A end time.

The Edge Gen module takes DPWMA and DPWMB from its own DPWM module, and the next one, and

uses them to generate edges for two outputs. For DPWM3, the DPWM0 is considered to be the next

DPWM. Each edge (rising and falling for DPWMA and DPWMB) has 8 options which can cause it.

The options are:

0 = DPWM(n) A Rising edge

1 = DPWM(n) A Falling edge

2 = DPWM(n) B Rising edge

3 = DPWM(n) B Falling edge

4 = DPWM(n+1) A Rising edge

5 = DPWM(n+1) A Falling edge

6 = DPWM(n+1) B Rising edge

7 = DPWM(n+1) B Falling edge

The Edge Gen is controlled by the DPWMEDGEGEN register. It also has an enable/disable bit.

The IntraMux is controlled by the Auto Config registers. Intra Mux is short for intra multiplexer. The

IntraMux takes signals from multiple DPWMs and from the Edge Gen and combines them logically to

generate DPWMA and DPWMB signals This is useful for topologies like phase-shifted full bridge,

especially when they are controlled with automatic mode switching. Of course, it can all be disabled, and

DPWMA and DPWMB will be driven as described in the sections above. If the Intra Mux is enabled, high

resolution must be disabled, and DPWM edge resolution goes down to 4 ns.

Here is a drawing of the Edge Gen/Intra Mux:

Here is a list of the IntraMux modes for DPWMA:

0 = DPWMA(n) pass through (default)

1 = Edge-gen output, DPWMA(n)

2 = DPWNC(n)

3 = DPWMB(n) (Crossover)

4 = DPWMA(n+1)

5 = DPWMB(n+1)

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