UCD3138 datasheet(28/68 Pages) TI1

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UCD3138

SLUSAP2 A – MARCH 2012 – REVISED MARCH 2012

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•

Shadow period register for end of period updates.

•

Quad-event

control

registers

and

rising

and

falling)

(Events

1-4)

– Used for on/off PWM duty ratio updates.

•

Phase control relative to other DPWM modules

•

Sample trigger placement for output voltage sensing at any point during the PWM cycle.

•

Support for 2 independent edge placement PWM outputs (same frequency or period setting)

•

Dead-time between PWM A and B outputs

•

High Resolution capabilities – 250 ps

•

Pulse cycle adjustment of up to ±8.192 µs ( 32768 × 250 ps)

•

Active high/ active low output polarity selection

•

Provides events to trigger both CPU interrupts and start of ADC conversions.

4.4.1.3

DPWM Events

Each DPWM can control the following timing events:

1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in

relationship to the PWM period. The programmed value set in the register should be one fourth of the

value calculated based on the PWM clock. As the DCLK (DCLK = 62.5 MHz max) controlling the

circuitry runs at one fourth of the PWM clock (PCLK = 250MHz max). When this sample trigger count

is equal to the PWM Counter, it initiates a front end calculation by triggering the EADC, resulting in a

CLA calculation, and a DPWM update. Over-sampling can be set for 2, 4 or 8 times the sampling rate.

2. Phase Trigger Count–count offset for slaving another DPWM (Multi-Phase/Interleaved operation).

3. Period–low resolution switching period count. (count of PCLK cycles)

4. Event 1–count offset for rising PWM A event. (Count of PCLK cycles)

5. Event 2–PWM count for falling PWM A event that sets the duty ratio. Last 4 bits of the register are for

high resolution control. Upper 14 bits are the number of PCLK cycle counts.

6. Event 3–PWM count for rising PWM B event. Last 4 bits of the register are for high resolution control.

Upper 14 bits are the number of PCLK cycle counts.

7. Event 4–PWM count for falling PWM B event. Last 4 bits of the register are for high resolution control.

Upper 14 bits are the number of PCLK cycle counts.

8. Cycle Adjust–Constant offset for Event 2 and Event 4 adjustments.

Basic comparisons between the programmed registers and the PWM counter can create the desired edge

placements in the DPWM. High resolution edge capability is available on Events 2, 3 and 4.

Functional Overview

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