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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HT45FM2C датащи(PDF) 40 Page - Holtek Semiconductor Inc |
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HT45FM2C датащи(HTML) 40 Page - Holtek Semiconductor Inc |
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40 / 171 page  Rev. 1.10 40 �a� �0� �01� Rev. 1.10 41 �a� �0� �01� HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Preliminar� Control Register Asingleregister,SMOD,isusedforoverallcontroloftheinternalclockswithinthisdevice. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS� CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLK R/W R/W R/W R/W R/W R R R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7~5 CKS2~CKS0: ThesystemclockselectionwhenHLCLKis“0” 000: fL(fLIRC) 001: fL(fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.In additiontothesystemclocksource,whichcanbetheLIRC,adividedversionofthe highspeedsystemoscillatorcanalsobechosenasthesystemclocksource. Bit 4 FSTEN: FastWake-upControl 0:Disable 1:Enable ThisistheFastWake-upControlbitwhichdeterminesifthefSUBclocksourceis initiallyusedafterthisdevicewakeup.Whenthebitishigh,thefSUBclocksourcecan beusedasatemporarysystemclocktoprovideafasterwakeuptimeasthefSUBclock isavailable. Bit 3 LTO: Lowspeedsystemoscillatorreadyflag 0:Notready 1:Ready Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeed systemoscillatorisstableafterpoweronresetorawake-uphasoccurred.Theflag willchangetoahighlevelafter1~2clockcyclesiftheLIRCoscillatorisused. Bit 2 HTO: Highspeedsystemoscillatorreadyflag 0:Notready 1:Ready Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeed systemoscillatorisstable.Thisflagisclearedto“0”byhardwarewhenthisdeviceis poweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatoris stable.Thereforethisflagwillalwaysbereadas“1”bytheapplicationprogramafter devicepower-on.TheflagwillbelowwhenintheSLEEPorIDLE0Modebutaftera wake-uphasoccurred,theflagwillchangetoahighlevelafter15~16clockcyclesif theHIRCoscillatorisused. Bit 1 IDLEN: IDLEModecontrol 0:Disable 1:Enable ThisistheIDLEModeControlbitanddetermineswhathappenswhentheHALT instructionisexecuted.Ifthisbitishigh,whenaHALTinstructionisexecutedthis devicewillentertheIDLEMode.IntheIDLE1ModetheCPUwillstoprunning butthesystemclockwillcontinuetokeeptheperipheralfunctionsoperational,if FSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstop inIDLE0Mode.IfthebitislowthisdevicewillentertheSLEEPModewhenaHALT instructionisexecuted. |
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