HT67F60 datasheet(98/242 Pages) HOLTEK

98 / 242 page

Rev. 1.50

March 06 , 2012

Rev. 1.50

March 06 , 2012

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPRO

I/O Pin Structures

The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the

exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide

only to assist with the functional understanding of the I/O pins. The wide range of pin-shared

structures does not permit all types to be shown.

Programming Considerations

Within the user program, one of the first things to consider is port initialisation. After a reset, all of

the I/O data and port control registers will be set high. This means that all I/O pins will default to an

input state, the level of which depends on the other connected circuitry and whether pull-high

selections have been chosen. If the port control registers, PAC~PHC, are then programmed to setup

some pins as outputs, these output pins will have an initial high output value unless the associated

port data registers, PA~PH, are first programmed. Selecting which pins are inputs and which are

outputs can be achieved byte-wide by loading the correct values into the appropriate port control

“CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write

operation takes place. The microcontroller must first read in the data on the entire port, modify it to

the required new bit values and then rewrite this data back to the output ports.

Port A has the additional capability of providing wake-up functions. When the device is in the

SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high

to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this

function.

V DD

Wa ke - up Se le ct

S yst em W ak e- up

Re ad D at a Re gi st er

C ont ro l Bi t

Da ta B us

Wr it e C ont ro l R egi st er

Ch ip R es et

Re ad C on tr ol R egi st er

Wr it e Da ta R egi st er

Da ta B it

I/O p in

PA o nl y

We ak

Pu ll- up

Pu ll -H ig h

R egi st er

Se le ct

Generic Input/Output Structure

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